): Boolean {
    return if (testCoverage.os == Os.MACOS && testCoverage.arch == Arch.AMD64) {
        subprojectName.contains("native") ||
            // Include precondition-tester here so we understand that tests do run on macOS intel as well
            subprojectName in listOf("file-watching", "snapshots", "workers", "logging", "precondition-tester")
    } else {
        true
    }

        assertEquals(UserAgentType.FIREFOX, userAgentHelper.getUserAgentType());
    }

    public void test_getUserAgentType_Safari() {
        getMockRequest().addHeader("user-agent",
                "Mozilla/5.0 (Macintosh; Intel Mac OS X 10_10_5) AppleWebKit/600.8.9 (KHTML, like Gecko) Version/8.0.8 Safari/600.8.9");
        assertEquals(UserAgentType.SAFARI, userAgentHelper.getUserAgentType());
    }

    public void test_getUserAgentType_Opera() {

## GNU/Linux

Use the following command to run a standalone MinIO server on Linux hosts running 64-bit Intel/AMD architectures. Replace ``/data`` with the path to the drive or directory in which you want MinIO to store data.

```sh
wget https://dl.min.io/server/minio/release/linux-amd64/minio
chmod +x minio
./minio server /data

# LINT.IfChange
package_group(name = "structured_tensor_allowlist")
# LINT.ThenChange(copy.bara.sky)

filegroup(
    name = "intel_binary_blob",
    data = if_mkl_ml(
        [
            "@local_xla//xla/tsl/mkl:intel_binary_blob",
        ],
    ),
)

bzl_library(
    name = "tensorflow_bzl",
    srcs = ["tensorflow.bzl"],

tool. For application developers, see <https://min.io/docs/minio/linux/developers/minio-drivers.html> to view MinIO SDKs for supported languages. ## GNU/Linux Use the following command to run a standalone MinIO server on Linux hosts running 64-bit Intel/AMD architectures. Replace ``/data`` with the path to the drive or directory in which you want MinIO to store data. ```sh wget https://dl.min.io/server/minio/release/linux-amd64/minio chmod +x minio ./minio server /data ``` The following table lists...

// For ARM, only R0 through R15 may appear.
// For ARM64, V0 through V31 with arrangement may appear.
//
// For 386/AMD64 register list specifies 4VNNIW-style multi-source operand.
// For range of 4 elements, Intel manual uses "+3" notation, for example:
//
//	VP4DPWSSDS zmm1{k1}{z}, zmm2+3, m128
//
// Given asm line:
//
//	VP4DPWSSDS Z5, [Z10-Z13], (AX)
//

            AVX512_BF16, AMX, etc.
            ([Intel Cascade Lake](https://www.intel.com/content/www/us/en/products/platforms/details/cascade-lake.html)
            and newer CPUs.)
            *   [Example performance speedups.](https://medium.com/intel-analytics-software/leverage-intel-deep-learning-optimizations-in-tensorflow-129faa80ee07)