VPCONFLICTQ 7(AX)(CX*8), K4, Y1                    // 62f2fd2cc48cc807000000
	VPCONFLICTQ Z27, K7, Z3                            // 6292fd4fc4db
	VPCONFLICTQ Z15, K7, Z3                            // 62d2fd4fc4df
	VPCONFLICTQ 7(AX)(CX*4), K7, Z3                    // 62f2fd4fc49c8807000000
	VPCONFLICTQ 7(AX)(CX*1), K7, Z3                    // 62f2fd4fc49c0807000000

	VAESENCLAST (AX), X16, X23                         // 62e27d00dd38 or 62e2fd00dd38
	VAESENCLAST 7(SI), X16, X23                        // 62e27d00ddbe07000000 or 62e2fd00ddbe07000000
	VAESENCLAST X23, X23, X23                          // 62a24500ddff or 62a2c500ddff
	VAESENCLAST X11, X23, X23                          // 62c24500ddfb or 62c2c500ddfb
	VAESENCLAST X31, X23, X23                          // 62824500ddff or 6282c500ddff

	{"$~(1<<63)", "$9223372036854775807"},
	{"$~0x3F", "$-64"},
	{"$~15", "$-16"},
	{"(((8)&0xf)*4)(SP)", "32(SP)"},
	{"(((8-14)&0xf)*4)(SP)", "40(SP)"},
	{"(6+8)(AX)", "14(AX)"},
	{"(8*4)(BP)", "32(BP)"},
	{"(AX)", "(AX)"},
	{"(AX)(CX*8)", "(AX)(CX*8)"},
	{"(BP)(CX*4)", "(BP)(CX*4)"},
	{"(BP)(DX*4)", "(BP)(DX*4)"},
	{"(BP)(R8*4)", "(BP)(R8*4)"},
	{"(BX)", "(BX)"},
	{"(DI)", "(DI)"},

	VPDPBUSDS 7(AX)(CX*4), X14, K4, X19                // 62e20d0c519c8807000000
	VPDPBUSDS 7(AX)(CX*1), X14, K4, X19                // 62e20d0c519c0807000000
	VPDPBUSDS X25, X0, K4, X19                         // 62827d0c51d9
	VPDPBUSDS X11, X0, K4, X19                         // 62c27d0c51db
	VPDPBUSDS X17, X0, K4, X19                         // 62a27d0c51d9

	VPMULTISHIFTQB 7(AX)(CX*4), Z2, K7, Z18            // 62e2ed4f83948807000000
	VPMULTISHIFTQB 7(AX)(CX*1), Z2, K7, Z18            // 62e2ed4f83940807000000
	VPMULTISHIFTQB Z7, Z21, K7, Z18                    // 62e2d54783d7
	VPMULTISHIFTQB Z13, Z21, K7, Z18                   // 62c2d54783d5
	VPMULTISHIFTQB 7(AX)(CX*4), Z21, K7, Z18           // 62e2d54783948807000000

	VPMADD52LUQ Z13, Z21, K7, Z8                       // 6252d547b4c5
	VPMADD52LUQ 7(AX), Z21, K7, Z8                     // 6272d547b48007000000
	VPMADD52LUQ (DI), Z21, K7, Z8                      // 6272d547b407
	VPMADD52LUQ Z16, Z5, K7, Z8                        // 6232d54fb4c0
	VPMADD52LUQ Z13, Z5, K7, Z8                        // 6252d54fb4c5
	VPMADD52LUQ 7(AX), Z5, K7, Z8                      // 6272d54fb48007000000

	VPOPCNTW Z13, K3, Z12                              // 6252fd4b54e5
	VPOPCNTW 7(AX), K3, Z12                            // 6272fd4b54a007000000
	VPOPCNTW (DI), K3, Z12                             // 6272fd4b5427
	VPOPCNTW Z28, K3, Z16                              // 6282fd4b54c4
	VPOPCNTW Z13, K3, Z16                              // 62c2fd4b54c5
	VPOPCNTW 7(AX), K3, Z16                            // 62e2fd4b548007000000

For example, the sequence to load <code>g</code> and <code>m</code>
using <code>CX</code> looks like this:
</p>

<pre>
#include "go_tls.h"
#include "go_asm.h"
...
get_tls(CX)
MOVL	g(CX), AX     // Move g into AX.
MOVL	g_m(AX), BX   // Move g.m into BX.
</pre>

<p>
The <code>get_tls</code> macro is also defined on <a href="#amd64">amd64</a>.
</p>

<p>
Addressing modes:
</p>

<ul>

<li>

			}
			if tok == scanner.EOF {
				p.errorf("unexpected EOF")
				return "", "", nil, false
			}
			// Split operands on comma. Also, the old syntax on x86 for a "register pair"
			// was AX:DX, for which the new syntax is DX, AX. Note the reordering.
			if tok == '\n' || tok == ';' || (nesting == 0 && (tok == ',' || tok == ':')) {
				if tok == ':' {
					// Remember this location so we can swap the operands below.

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