AANDN
	AORN
	AXNOR
	ACLZ
	ACLZW
	ACTZ
	ACTZW
	ACPOP
	ACPOPW
	AMAX
	AMAXU
	AMIN
	AMINU
	ASEXTB
	ASEXTH
	AZEXTH

	// 1.3: Bitwise Rotation (Zbb)
	AROL
	AROLW
	AROR
	ARORI
	ARORIW
	ARORW
	AORCB
	AREV8

	// 1.5: Single-bit Instructions (Zbs)
	ABCLR
	ABCLRI
	ABEXT
	ABEXTI
	ABINV
	ABINVI
	ABSET
	ABSETI

	ARDPKRU
	ARDPMC
	ARDRANDL
	ARDRANDQ
	ARDRANDW
	ARDSEEDL
	ARDSEEDQ
	ARDSEEDW
	ARDTSC
	ARDTSCP
	AREP
	AREPN
	ARETFL
	ARETFQ
	ARETFW
	AROLB
	AROLL
	AROLQ
	AROLW
	ARORB
	ARORL
	ARORQ
	ARORW
	ARORXL
	ARORXQ
	AROUNDPD
	AROUNDPS
	AROUNDSD
	AROUNDSS
	ARSM
	ARSQRTPS
	ARSQRTSS
	ASAHF
	ASALB
	ASALL
	ASALQ
	ASALW
	ASARB

		return &inst{0x3b, 0x7, 0x0, 32, 0x1}
	case AREMW:
		return &inst{0x3b, 0x6, 0x0, 32, 0x1}
	case AREV8:
		return &inst{0x13, 0x5, 0x18, 1720, 0x35}
	case AROL:
		return &inst{0x33, 0x1, 0x0, 1536, 0x30}
	case AROLW:
		return &inst{0x3b, 0x1, 0x0, 1536, 0x30}
	case AROR:
		return &inst{0x33, 0x5, 0x0, 1536, 0x30}
	case ARORI:
		return &inst{0x13, 0x5, 0x0, 1536, 0x30}
	case ARORIW:
		return &inst{0x1b, 0x5, 0x0, 1536, 0x30}

		// Rotation instructions are supported natively.
		return []*instruction{ins}
	}

	switch ins.as {
	case AROL, AROLW, AROR, ARORW:
		// ROL -> OR (SLL x y) (SRL x (NEG y))
		// ROR -> OR (SRL x y) (SLL x (NEG y))
		sllOp, srlOp := ASLL, ASRL
		if ins.as == AROLW || ins.as == ARORW {
			sllOp, srlOp = ASLLW, ASRLW
		}
		shift1, shift2 := sllOp, srlOp
		if ins.as == AROR || ins.as == ARORW {

	{AROLB, yshb, Pb, opBytes{0xd0, 00, 0xc0, 00, 0xd2, 00}},
	{AROLL, yshl, Px, opBytes{0xd1, 00, 0xc1, 00, 0xd3, 00, 0xd3, 00}},
	{AROLQ, yshl, Pw, opBytes{0xd1, 00, 0xc1, 00, 0xd3, 00, 0xd3, 00}},
	{AROLW, yshl, Pe, opBytes{0xd1, 00, 0xc1, 00, 0xd3, 00, 0xd3, 00}},
	{ARORB, yshb, Pb, opBytes{0xd0, 01, 0xc0, 01, 0xd2, 01}},
	{ARORL, yshl, Px, opBytes{0xd1, 01, 0xc1, 01, 0xd3, 01, 0xd3, 01}},

				{0, 239}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ROLW",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		asm:          x86.AROLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, 2},   // CX
				{0, 239}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, 239}, // AX CX DX BX BP SI DI
			},
		},
	},