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Results 1 - 10 of 17 for 4xi16 (0.09 sec)
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tensorflow/compiler/mlir/lite/tests/flatbuffer2mlir/constants_offset.mlir
func.return %0 : tensor<4xi8> } func.func @i16() -> tensor<4xi16> { // CHECK-LABEL: @i16 // CHECK: value = dense<[1, 2, 3, 258]> : tensor<4xi16> %0 = "tfl.pseudo_const" () { value = dense<[1, 2, 3, 258]> : tensor<4xi16> } : () -> tensor<4xi16> func.return %0 : tensor<4xi16> } func.func @i32() -> tensor<4xi32> { // CHECK-LABEL: @i32
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 12.1K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/flatbuffer2mlir/constants.mlir
func.return %0 : tensor<4xi8> } func.func @i16() -> tensor<4xi16> { // CHECK-LABEL: @i16 // CHECK: value = dense<[1, 2, 3, 258]> : tensor<4xi16> %0 = "tfl.pseudo_const" () { value = dense<[1, 2, 3, 258]> : tensor<4xi16> } : () -> tensor<4xi16> func.return %0 : tensor<4xi16> } func.func @i32() -> tensor<4xi32> { // CHECK-LABEL: @i32
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 12.1K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/const-fold.mlir
%8 = "tfl.mul"(%2, %3) {fused_activation_function = "NONE"} : (tensor<4xf16>, tensor<4xf16>) -> tensor<4xf16> func.return %5, %6, %7, %8 : tensor<f16>, tensor<4xf16>, tensor<4xf16>, tensor<4xf16> } // CHECK-LABEL: @elementwise_unary_ops func.func @elementwise_unary_ops() -> (tensor<f32>, tensor<f32>, tensor<f32>, tensor<f32>, tensor<f32>, tensor<f32>, tensor<f32>) {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 45.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/legalize-tf.mlir
} func.func @floor_mod_i16(%arg0: tensor<5xi16>, %arg1: tensor<5xi16>) -> tensor<5xi16> { %0 = "tf.FloorMod"(%arg0, %arg1) : (tensor<5xi16>, tensor<5xi16>) -> tensor<5xi16> func.return %0 : tensor<5xi16> // CHECK-LABEL: floor_mod_i16 // CHECK: "tfl.floor_mod"(%arg0, %arg1) : (tensor<5xi16>, tensor<5xi16>) -> tensor<5xi16> } func.func @exp(%arg0: tensor<5xf32>) -> tensor<5xf32> {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Jun 05 01:54:33 UTC 2024 - 153.4K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/mlir2flatbuffer/logical.mlir
%1 = "tfl.pseudo_const" () {value = dense<false> : tensor<4xi1>} : () -> tensor<4xi1> loc("Const2") %2 = "tfl.logical_or"(%arg0, %1) : (tensor<4xi1>, tensor<4xi1>) -> tensor<4xi1> loc("logical_or") %3 = "tfl.logical_and"(%2, %0) : (tensor<4xi1>, tensor<4xi1>) -> tensor<4xi1> loc("logical_and") func.return %3 : tensor<4xi1>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Jul 14 16:41:28 UTC 2022 - 3.6K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/mlir2graphdef/shape_list_attr.mlir
// CHECK: shape { // CHECK-NEXT: unknown_rank: true func.func @main() { tf_executor.graph { %0:4 = tf_executor.island wraps "tf.InfeedDequeueTuple"() : () -> (tensor<3xi32>, tensor<4x?xf32>, tensor<*xi16>) tf_executor.fetch } func.return
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Mar 28 12:06:33 UTC 2022 - 931 bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/tf_device_ops.mlir
%8 = "tf.opI"() : () -> tensor<*xf32> %9 = "tf.opJ"() : () -> tensor<*xi8> %10 = "tf.opK"() : () -> tensor<*xi16> %11 = "tf.opL"() : () -> tensor<*xi64> tf_device.replicate([%0, %1, %2] as %input0: tensor<*xi1>, %9 as %input1: tensor<*xi8>, %10 as %input2: tensor<*xi16>, [%3, %4, %5] as %input3: tensor<*xi32>, [%6, %7, %8] as %input4: tensor<*xf32>, %11 as %input5: tensor<*xi64>) {n = 3 : i32} { tf_device.return }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jan 23 23:53:20 UTC 2024 - 7.7K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/functional-control-flow-to-cfg.mlir
} // ----- // If with a 4xi1 condition. func.func private @testIf1Then(tensor<*xf32>, tensor<*xf32>) -> tensor<*xf32> func.func private @testIf1Else(tensor<*xf32>, tensor<*xf32>) -> tensor<*xf32> // CHECK-LABEL: func @testIf1x4 func.func @testIf1x4(tensor<4xi1>, tensor<*xf32>, tensor<*xf32>) -> tensor<*xf32> { ^bb0(%arg0: tensor<4xi1>, %arg1: tensor<*xf32>, %arg2: tensor<*xf32>):
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 12.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/graphdef2mlir/shape-attrs.pbtxt
value { type: DT_BOOL } } } # CHECK-DAG: tf.IteratorGetNext{{.+}}-> (tensor<1x8xbf16>, tensor<2x?x16xf32>, tensor<*xf64>) # CHECK-DAG: tf.IteratorGetNextSync{{.+}}-> (tensor<*xi16>, tensor<3x24xi32>, tensor<?x4x32xi64>) # CHECK-DAG: tf.MultiDeviceIteratorGetNextFromShard{{.+}}-> (tensor<5x40xf16>, tensor<*xcomplex<f32>>, tensor<6x48x?xcomplex<f64>>)
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri Dec 04 18:02:53 UTC 2020 - 5K bytes - Viewed (0) -
tensorflow/compiler/mlir/tf2xla/tests/legalize-tf.mlir
// CHECK: %[[REDUCED:.*]] = mhlo.reduce(%[[CAST]] init: %[[INITIAL]]) applies mhlo.maximum across dimensions = [1] : (tensor<4x8xf16>, tensor<f16>) -> tensor<4xf16> // CHECK: %[[CAST_BACK:.*]] = mhlo.convert %[[REDUCED]] : tensor<4xf16> // CHECK: %[[RESULT:.*]] = mhlo.reshape %[[CAST_BACK]] : (tensor<4xf16>) -> tensor<4x1xf16> // CHECK: return %[[RESULT]] : tensor<4x1xf16>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon May 06 18:46:23 UTC 2024 - 335.5K bytes - Viewed (0)