//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	DIV	R18, R22	// 02d2001a
	DIVU	R14, R9		// 012e001b
	DIVV	R8, R13		// 01a8001e
	DIVVU	R16, R19	// 0270001f

//	LREM rreg ',' rreg
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	REM	R18, R22	// 02d2001a
	REMU	R14, R9		// 012e001b
	REMV	R8, R13		// 01a8001e
	REMVU	R16, R19	// 0270001f

//	LSHW rreg ',' sreg ',' rreg
//	{

}

// IsLoong64MUL reports whether the op (as defined by an loong64.A* constant) is
// one of the MUL/DIV/REM instructions that require special handling.
func IsLoong64MUL(op obj.As) bool {
	switch op {
	case loong64.AMUL, loong64.AMULU, loong64.AMULV, loong64.AMULVU,
		loong64.ADIV, loong64.ADIVU, loong64.ADIVV, loong64.ADIVVU,
		loong64.AREM, loong64.AREMU, loong64.AREMV, loong64.AREMVU:
		return true
	}
	return false
}

	rec, nl, rem := rest[:n-1], rest[n-1:n], rest[n:]
	if nl != "\n" {
		return "", "", s, ErrHeader
	}

	// The first equals separates the key from the value.
	k, v, ok = strings.Cut(rec, "=")
	if !ok {
		return "", "", s, ErrHeader
	}

	if !validPAXRecord(k, v) {
		return "", "", s, ErrHeader
	}
	return k, v, rem, nil
}

pkg hash/maphash, type Hash struct
pkg hash/maphash, type Seed struct
pkg log, const Lmsgprefix = 64
pkg log, const Lmsgprefix ideal-int
pkg math, func FMA(float64, float64, float64) float64
pkg math/bits, func Rem(uint, uint, uint) uint
pkg math/bits, func Rem32(uint32, uint32, uint32) uint32
pkg math/bits, func Rem64(uint64, uint64, uint64) uint64
pkg mime/multipart, method (*Reader) NextRawPart() (*Part, error)

pkg go/token, const QUO Token
pkg go/token, const QUO_ASSIGN Token
pkg go/token, const RANGE Token
pkg go/token, const RBRACE Token
pkg go/token, const RBRACK Token
pkg go/token, const REM Token
pkg go/token, const REM_ASSIGN Token
pkg go/token, const RETURN Token
pkg go/token, const RPAREN Token
pkg go/token, const SELECT Token
pkg go/token, const SEMICOLON Token
pkg go/token, const SHL Token

	MULU	R4, R5	   		// a5101c00
	MULU	R4, R5, R6		// a6101c00
	MULH	R4, R5	   		// a5901c00
	MULH	R4, R5, R6	   	// a6901c00
	MULHU	R4, R5			// a5101d00
	MULHU	R4, R5, R6		// a6101d00
	REM	R4, R5	  		// a5902000
	REM	R4, R5, R6	  	// a6902000
	REMU	R4, R5	   		// a5902100
	REMU	R4, R5, R6	   	// a6902100
	DIV	R4, R5	  		// a5102000
	DIV	R4, R5, R6	  	// a6102000
	DIVU	R4, R5	   		// a5102100

	MULH	X5, X6, X7				// b3135302
	MULHU	X5, X6, X7				// b3335302
	MULHSU	X5, X6, X7				// b3235302
	MULW	X5, X6, X7				// bb035302
	DIV	X5, X6, X7				// b3435302
	DIVU	X5, X6, X7				// b3535302
	REM	X5, X6, X7				// b3635302
	REMU	X5, X6, X7				// b3735302
	DIVW	X5, X6, X7				// bb435302
	DIVUW	X5, X6, X7				// bb535302
	REMW	X5, X6, X7				// bb635302
	REMUW	X5, X6, X7				// bb735302

	DIVDE R3, R4, R5                // 7ca41b52
	DIVDECC R3, R4, R5              // 7ca41b53
	DIVDEU R3, R4, R5               // 7ca41b12
	DIVDEUCC R3, R4, R5             // 7ca41b13

	REM R3, R4, R5                  // 7fe41bd67fff19d67cbf2050
	REMU R3, R4, R5                 // 7fe41b967fff19d67bff00287cbf2050
	REMD R3, R4, R5                 // 7fe41bd27fff19d27cbf2050