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Results 1 - 4 of 4 for 1x64x128x128xf32 (0.12 sec)
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tensorflow/compiler/mlir/lite/stablehlo/tests/legalize_hlo.mlir
// CHECK: return %[[VAL_9:.*]] : tensor<1x64x128x128xf32> // CHECK: } func.func @convert_transpose_conv_with_transpose(%arg0: tensor<1x256x64x64xf32>, %arg1: tensor<2x2x64x256xf32>) -> tensor<1x64x128x128xf32> { %0 = "mhlo.convolution"(%arg0, %arg1) {batch_group_count = 1 : i64,
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed May 29 07:26:59 UTC 2024 - 340.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_to_nhwc.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 4.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_gpu_cc_70.mlir
-> tensor<1x26x26x64xf32> func.return %0 : tensor<1x26x26x64xf32> } // CHECK-LABEL: func @transposeConv2D_1x1_f32 func.func @transposeConv2D_1x1_f32(%input: tensor<1x64x28x28xf32>, %filter: tensor<1x1x64x64xf32>) -> tensor<1x64x28x28xf32> { // 1x1 convolution can be computed as a GEMM in NHWC data format. // CHECK: "tf.Conv2D"(%[[INPUT_TRANSPOSE:[0-9]*]], %arg1) // CHECK-SAME: data_format = "NHWC"
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 21 08:41:18 UTC 2022 - 8.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_to_nchw.mlir
// CHECK: "tf.FusedBatchNormGradV3" // CHECK-SAME: (%[[ARG0_TPOSE]], %[[ARG1_TPOSE]], %arg2, %arg2, %arg2, %arg2) // CHECK-SAME: data_format = "NCHW" // CHECK-SAME: (tensor<1x64x28x28xf32>, tensor<1x64x28x28xf32>, // CHECK-SAME: -> (tensor<1x64x28x28xf32>, // CHECK: %[[RES_PERM:.*]] = "tf.Const"() // CHECK-SAME: <{value = dense<[0, 2, 3, 1]> : tensor<4xi64>}> // CHECK: %[[RES_TPOSE:[0-9]*]] = "tf.Transpose"
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 9K bytes - Viewed (0)