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Results 1 - 5 of 5 for vcmpequq (3.05 sec)
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src/cmd/internal/obj/ppc64/anames.go
"VSLDOI", "VCLZ", "VCLZB", "VCLZH", "VCLZW", "VCLZD", "VPOPCNT", "VPOPCNTB", "VPOPCNTH", "VPOPCNTW", "VPOPCNTD", "VCMPEQ", "VCMPEQUB", "VCMPEQUBCC", "VCMPEQUH", "VCMPEQUHCC", "VCMPEQUW", "VCMPEQUWCC", "VCMPEQUD", "VCMPEQUDCC", "VCMPGT", "VCMPGTUB", "VCMPGTUBCC", "VCMPGTUH", "VCMPGTUHCC", "VCMPGTUW", "VCMPGTUWCC", "VCMPGTUD",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/a.out.go
AVSOI AVSLDOI AVCLZ AVCLZB AVCLZH AVCLZW AVCLZD AVPOPCNT AVPOPCNTB AVPOPCNTH AVPOPCNTW AVPOPCNTD AVCMPEQ AVCMPEQUB AVCMPEQUBCC AVCMPEQUH AVCMPEQUHCC AVCMPEQUW AVCMPEQUWCC AVCMPEQUD AVCMPEQUDCC AVCMPGT AVCMPGTUB AVCMPGTUBCC AVCMPGTUH AVCMPGTUHCC AVCMPGTUW AVCMPGTUWCC AVCMPGTUD AVCMPGTUDCC AVCMPGTSB
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 16K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm9.go
case AVCMPEQUB: return OPVC(4, 6, 0, 0) /* vcmpequb - v2.03 */ case AVCMPEQUBCC: return OPVC(4, 6, 0, 1) /* vcmpequb. - v2.03 */ case AVCMPEQUH: return OPVC(4, 70, 0, 0) /* vcmpequh - v2.03 */ case AVCMPEQUHCC: return OPVC(4, 70, 0, 1) /* vcmpequh. - v2.03 */ case AVCMPEQUW: return OPVC(4, 134, 0, 0) /* vcmpequw - v2.03 */ case AVCMPEQUWCC:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 13:55:28 UTC 2024 - 156.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
VPOPCNTD V1, V2 // 10400fc3 VCMPEQUB V1, V2, V3 // 10611006 VCMPEQUBCC V1, V2, V3 // 10611406 VCMPEQUH V1, V2, V3 // 10611046 VCMPEQUHCC V1, V2, V3 // 10611446 VCMPEQUW V1, V2, V3 // 10611086 VCMPEQUWCC V1, V2, V3 // 10611486 VCMPEQUD V1, V2, V3 // 106110c7 VCMPEQUDCC V1, V2, V3 // 106114c7
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/crypto/internal/nistec/p256_asm_ppc64le.s
MOVD $32, R17 MOVD $48, R18 MOVD $56, R21 MOVD $64, R19 MOVD $80, R20 // cond is R1 + 24 (cond offset) + 32 LXVDSX (R1)(R21), SEL VSPLTISB $0, ZER // SEL controls whether to store a or b VCMPEQUD SEL, ZER, SEL LXVD2X (P1ptr+R0), X1H LXVD2X (P1ptr+R16), X1L LXVD2X (P1ptr+R17), Y1H LXVD2X (P1ptr+R18), Y1L LXVD2X (P1ptr+R19), Z1H LXVD2X (P1ptr+R20), Z1L LXVD2X (P2ptr+R0), X2H
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 56.5K bytes - Viewed (0)