return "", false
	}
	archCaps = fileArch
	fileArch = strings.ToLower(fileArch)
	fileArch = strings.TrimSuffix(fileArch, "splitload")
	fileArch = strings.TrimSuffix(fileArch, "latelower")
	if fileArch == goArch {
		return "", false
	}
	if fileArch == strings.TrimSuffix(goArch, "le") {
		return "", false
	}
	return archCaps, true
}

		disabled: !buildcfg.Experiment.PreemptibleLoops}, // insert resched checks in loops.
	{name: "lower", fn: lower, required: true},
	{name: "addressing modes", fn: addressingModes, required: false},
	{name: "late lower", fn: lateLower, required: true},
	{name: "lowered deadcode for cse", fn: deadcode}, // deadcode immediately before CSE avoids CSE making dead values live again
	{name: "lowered cse", fn: cse},
	{name: "elim unread autos", fn: elimUnreadAutos},

// n is always a zero-extended uint16 value, so n & z is always a non-negative 32 or 64 bit value.
// Rewrite to a cmp int64(0) to lower into ANDCCconst in the latelower pass.
(CMP(W|U|WU)const [0] a:(ANDconst [n] z)) => (CMPconst [0] a)

// SETBC auxInt values 0=LT 1=GT 2=EQ   Crbit==1 ? 1 : 0
// SETBCR auxInt values 0=LT 1=GT 2=EQ   Crbit==1 ? 0 : 1
(Equal cmp) => (SETBC [2] cmp)

// Copyright 2022 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

// This file contains rules used by the laterLower pass.
// These are often the exact inverse of rules in ARM64.rules.

(ADDconst [c] x) && !isARM64addcon(c)  => (ADD x (MOVDconst [c]))
(SUBconst [c] x) && !isARM64addcon(c)  => (SUB x (MOVDconst [c]))

// Copyright 2022 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

// This file contains rules used by the laterLower pass.

// Simplify ISEL x $0 z into ISELZ
(ISEL [a] x (MOVDconst [0]) z) => (ISELZ [a] x z)
// Simplify ISEL $0 y z into ISELZ by inverting comparison and reversing arguments.
(ISEL [a] (MOVDconst [0]) y z) => (ISELZ [a^0x4] y z)