Instead, the compiler operates on a kind of semi-abstract instruction set,
and instruction selection occurs partly after code generation.
The assembler works on the semi-abstract form, so
when you see an instruction like <code>MOV</code>
what the toolchain actually generates for that operation might
not be a move instruction at all, perhaps a clear or load.
Or it might correspond exactly to the machine instruction with that name.

		}
		p.errorf("wrong number of arguments to %s instruction", op)
		return
	case 4:
		if p.arch.Family == sys.S390X || p.arch.Family == sys.PPC64 {
			// 4-operand compare-and-branch.
			prog.From = a[0]
			prog.Reg = p.getRegister(prog, op, &a[1])
			prog.AddRestSource(a[2])
			target = &a[3]
			break
		}
		p.errorf("wrong number of arguments to %s instruction", op)
		return
	default:

const (
	RFP = -(iota + 1)
	RSB
	RSP
	RPC
)

// Arch wraps the link architecture object with more architecture-specific information.
type Arch struct {
	*obj.LinkArch
	// Map of instruction names to enumeration.
	Instructions map[string]obj.As
	// Map of register names to enumeration.
	Register map[string]int16
	// Table of register prefix names. These are things like R for R(0) and SPR for SPR(268).

				printed = note
			}
		case 3:
			// printed form, then hex
			printed = strings.TrimSpace(parts[1])
			hexes = strings.TrimSpace(parts[2])
			if !isHexes(hexes) {
				t.Errorf("%s:%d: malformed hex instruction encoding: %s", input, lineno, line)
			}
		}

		if hexes != "" {
			hexByLine[fmt.Sprintf("%s:%d", input, lineno)] = hexes
		}

		// Canonicalize spacing in printed form.

	// 31.13.8: Vector Floating-Point Square-Root Instruction
	VFSQRTV		V2, V3				// d711204e
	VFSQRTV		V2, V0, V3			// d711204c

	// 31.13.9: Vector Floating-Point Reciprocal Square-Root Estimate Instruction
	VFRSQRT7V	V2, V3				// d711224e
	VFRSQRT7V	V2, V0, V3			// d711224c

	// 31.13.10: Vector Floating-Point Reciprocal Estimate Instruction
	VFREC7V		V2, V3				// d791224e

// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

// This file encapsulates some of the odd characteristics of the ARM64
// instruction set, to minimize its interaction with the core of the
// assembler.

package arch

import (
	"cmd/internal/obj"
	"cmd/internal/obj/arm64"
	"errors"
)

var arm64LS = map[string]uint8{

	pendingLabels []string // Labels to attach to next instruction.
	labels        map[string]*obj.Prog
	toPatch       []Patch
	addr          []obj.Addr
	arch          *arch.Arch
	ctxt          *obj.Link
	firstProg     *obj.Prog
	lastProg      *obj.Prog
	dataAddr      map[string]int64 // Most recent address for DATA for this symbol.
	isJump        bool             // Instruction being assembled is a jump.

register_toolchains("@rules_ml_toolchain//cc:linux_aarch64_linux_aarch64_cuda")

# Initialize the TensorFlow repository and all dependencies.
#
# The cascade of load() statements and tf_workspace?() calls works around the
# restriction that load() statements need to be at the top of .bzl files.
# E.g. we can not retrieve a new repository with http_archive and then load()
# a macro from that repository in the same file.

	MOVWP	4(R5), R4		// a4040024
	MOVWP	(R5), R4		// a4000024
	MOVVP	32764(R5), R4		// a4fc7f26
	MOVVP	32(R5), R4		// a4200026
	MOVVP	4(R5), R4		// a4040026
	MOVVP	(R5), R4		// a4000026

	// ADDU16I.D instruction
	ADDV16	$(-32768<<16), R4, R5	// ADDV16	$-2147483648, R4, R5	// 85000012
	ADDV16	$(0<<16), R4, R5	// ADDV16	$0, R4, R5		// 85000010
	ADDV16	$(8<<16), R4, R5	// ADDV16	$524288, R4, R5		// 85200010

#
# Macosx options
#     darwin_arm64:
#
# Compiler options:
#     cuda_clang:             Use Clang when building CUDA code.
#     avx_linux:              Build with avx instruction set on linux.
#     avx_win:                Build with avx instruction set on windows
#
# Other build options:
#     short_logs:       Only log errors during build, skip warnings.
#     verbose_logs:     Show all compiler warnings during build.