K k5,
      V v5,
      K k6,
      V v6,
      K k7,
      V v7,
      K k8,
      V v8,
      K k9,
      V v9) {
    return new RegularImmutableBiMap<K, V>(
        ImmutableMap.of(k1, v1, k2, v2, k3, v3, k4, v4, k5, v5, k6, v6, k7, v7, k8, v8, k9, v9));
  }

  public static <K, V> ImmutableBiMap<K, V> of(
      K k1,
      V v1,
      K k2,
      V v2,
      K k3,

      V v7,
      K k8,
      V v8,
      K k9,
      V v9) {
    checkEntryNotNull(k1, v1);
    checkEntryNotNull(k2, v2);
    checkEntryNotNull(k3, v3);
    checkEntryNotNull(k4, v4);
    checkEntryNotNull(k5, v5);
    checkEntryNotNull(k6, v6);
    checkEntryNotNull(k7, v7);
    checkEntryNotNull(k8, v8);
    checkEntryNotNull(k9, v9);
    return new RegularImmutableBiMap<K, V>(

      K k7,
      V v7,
      K k8,
      V v8,
      K k9,
      V v9) {
    return new Builder<K, V>(Ordering.natural())
        .put(k1, v1)
        .put(k2, v2)
        .put(k3, v3)
        .put(k4, v4)
        .put(k5, v5)
        .put(k6, v6)
        .put(k7, v7)
        .put(k8, v8)
        .put(k9, v9)
        .build();
  }

	FMOVD	F1, ZR                          // 3f00669e
	FMOVS	F1, ZR                          // 3f00261e
	VUADDW	V9.B8, V12.H8, V14.H8           // 8e11292e
	VUADDW	V13.H4, V10.S4, V11.S4          // 4b116d2e
	VUADDW	V21.S2, V24.D2, V29.D2          // 1d13b52e
	VUADDW2	V9.B16, V12.H8, V14.H8          // 8e11296e
	VUADDW2	V13.H8, V20.S4, V30.S4          // 9e126d6e
	VUADDW2	V21.S4, V24.D2, V29.D2          // 1d13b56e

	VST1.P	[V4.S4], 8(R1)                                   // ERROR "invalid post-increment offset"
	VLD1.P	32(R1), [V8.S4, V9.S4, V10.S4]                   // ERROR "invalid post-increment offset"
	VLD1.P	48(R1), [V7.S4, V8.S4, V9.S4, V10.S4]            // ERROR "invalid post-increment offset"
	VPMULL	V1.D1, V2.H4, V3.Q1                              // ERROR "invalid arrangement"

      V v7,
      K k8,
      V v8,
      K k9,
      V v9) {
    return RegularImmutableBiMap.fromEntries(
        entryOf(k1, v1),
        entryOf(k2, v2),
        entryOf(k3, v3),
        entryOf(k4, v4),
        entryOf(k5, v5),
        entryOf(k6, v6),
        entryOf(k7, v7),
        entryOf(k8, v8),
        entryOf(k9, v9));
  }

  /**

      V v7,
      K k8,
      V v8,
      K k9,
      V v9,
      K k10,
      V v10) {
    return fromEntries(
        entryOf(k1, v1),
        entryOf(k2, v2),
        entryOf(k3, v3),
        entryOf(k4, v4),
        entryOf(k5, v5),
        entryOf(k6, v6),
        entryOf(k7, v7),
        entryOf(k8, v8),
        entryOf(k9, v9),
        entryOf(k10, v10));
  }

  /**

	VSLDB	$3, V1, V16, V18        // e72100030a77
	VERIMB	$2, V31, V1, V2         // e72f10020472
	VSEL	V1, V2, V3, V4          // e7412000308d
	VGFMAH	V21, V31, V24, V0       // e705f10087bc
	VFMADB	V16, V8, V9, V10        // e7a08300948f
	WFMADB	V17, V18, V19, V20      // e74123083f8f
	VFMSDB	V2, V25, V24, V31       // e7f293008b8e
	WFMSDB	V31, V2, V3, V4         // e74f2308348e
	VPERM	V31, V0, V2, V3         // e73f0000248c

	XVMOVQ		X27.V[0], X9    // 69e30377

	// Move vector element to vector.
	VMOVQ		V1.B[3], V9.B16 // 298cf772
	VMOVQ		V2.H[2], V8.H8  // 48c8f772
	VMOVQ		V3.W[1], V7.W4  // 67e4f772
	VMOVQ		V4.V[0], V6.V2  // 86f0f772

	// Move vector register to vector register.
	VMOVQ		V1, V9		// 29002d73
	VMOVQ		V2, V8		// 48002d73
	XVMOVQ		X3, X7		// 67002d77
	XVMOVQ		X4, X6		// 86002d77

) DO4_CIPHER(V0,V1,V2,V3,V8,R4,VCIPHERLAST) XOR_STORE(V9,V0,R5,R0) XOR_STORE(V10,V1,R5,R8) XOR_STORE(V11,V2,R5,R9) XOR_STORE(V12,V3,R5,R10) RET //func ctrBlocks8Asm(nr int, xk *[60]uint32, dst, src *[8 * BlockSize]byte, ivlo, ivhi uint64) TEXT ·ctrBlocks8Asm(SB), NOSPLIT|NOFRAME, $0 CTRBLOCK_PROLOGUE XXLEQV V8, V8, V8 // V8 is -1 VSUBUQM V0, V8, V1 // Vi = IV + i (as IV - (-1)) VADDUQM V8, V8, V9 // V9 is -2 VSUBUQM V0, V9, V2 VSUBUQM V1, V9, V3 VSUBUQM V2, V9, V4 VSUBUQM V3, V9, V5 VSUBUQM V4, V9,...