VST1.P	[V4.S4,V5.S4], 48(R1)                            // ERROR "invalid post-increment offset"
	VST1.P	[V4.S4], 8(R1)                                   // ERROR "invalid post-increment offset"
	VLD1.P	32(R1), [V8.S4, V9.S4, V10.S4]                   // ERROR "invalid post-increment offset"
	VLD1.P	48(R1), [V7.S4, V8.S4, V9.S4, V10.S4]            // ERROR "invalid post-increment offset"

	DMB	$1
	SVC

// encryption
	SHA256H	V9.S4, V3, V2                   // 6240095e
	SHA256H2	V9.S4, V4, V3           // 8350095e
	SHA256SU0	V8.S4, V7.S4            // 0729285e
	SHA256SU1	V6.S4, V5.S4, V7.S4     // a760065e
	SHA1SU0	V11.S4, V8.S4, V6.S4            // 06310b5e
	SHA1SU1	V5.S4, V1.S4                    // a118285e
	SHA1C	V1.S4, V2, V3                   // 4300015e

	}
}

// registerList parses an ARM or ARM64 register list expression, a list of
// registers in []. There may be comma-separated ranges or individual
// registers, as in [R1,R3-R5] or [V1.S4, V2.S4, V3.S4, V4.S4].
// For ARM, only R0 through R15 may appear.
// For ARM64, V0 through V31 with arrangement may appear.
//
// For 386/AMD64 register list specifies 4VNNIW-style multi-source operand.

		curQ = 0
	case "B16":
		curSize = 0
		curQ = 1
	case "H4":
		curSize = 1
		curQ = 0
	case "H8":
		curSize = 1
		curQ = 1
	case "S2":
		curSize = 2
		curQ = 0
	case "S4":
		curSize = 2
		curQ = 1
	case "D1":
		curSize = 3
		curQ = 0
	case "D2":
		curSize = 3
		curQ = 1
	default:
		return 0, errors.New("invalid arrangement in ARM64 register list")
	}

MOVD H0, curK octetsLoop: SUB $128, srcPtrLen VMOV CTR.B16, B0.B16 VADD B0.S4, INC.S4, B1.S4 VREV32 B0.B16, B0.B16 VADD B1.S4, INC.S4, B2.S4 VREV32 B1.B16, B1.B16 VADD B2.S4, INC.S4, B3.S4 VREV32 B2.B16, B2.B16 VADD B3.S4, INC.S4, B4.S4 VREV32 B3.B16, B3.B16 VADD B4.S4, INC.S4, B5.S4 VREV32 B4.B16, B4.B16 VADD B5.S4, INC.S4, B6.S4 VREV32 B5.B16, B5.B16 VADD B6.S4, INC.S4, B7.S4 VREV32 B6.B16, B6.B16 VADD B7.S4, INC.S4, CTR.S4 VREV32 B7.B16, B7.B16 aesrndx8(K0) aesrndx8(K1) aesrndx8(K2) aesrndx8(K3)...

MOVD H0, curK octetsLoop: SUB $128, srcPtrLen VMOV CTR.B16, B0.B16 VADD B0.S4, INC.S4, B1.S4 VREV32 B0.B16, B0.B16 VADD B1.S4, INC.S4, B2.S4 VREV32 B1.B16, B1.B16 VADD B2.S4, INC.S4, B3.S4 VREV32 B2.B16, B2.B16 VADD B3.S4, INC.S4, B4.S4 VREV32 B3.B16, B3.B16 VADD B4.S4, INC.S4, B5.S4 VREV32 B4.B16, B4.B16 VADD B5.S4, INC.S4, B6.S4 VREV32 B5.B16, B5.B16 VADD B6.S4, INC.S4, B7.S4 VREV32 B6.B16, B6.B16 VADD B7.S4, INC.S4, CTR.S4 VREV32 B7.B16, B7.B16 aesrndx8(K0) aesrndx8(K1) aesrndx8(K2) aesrndx8(K3)...

	register["A4"] = riscv.REG_A4
	register["A5"] = riscv.REG_A5
	register["A6"] = riscv.REG_A6
	register["A7"] = riscv.REG_A7
	register["S2"] = riscv.REG_S2
	register["S3"] = riscv.REG_S3
	register["S4"] = riscv.REG_S4
	register["S5"] = riscv.REG_S5
	register["S6"] = riscv.REG_S6
	register["S7"] = riscv.REG_S7
	register["S8"] = riscv.REG_S8
	register["S9"] = riscv.REG_S9
	register["S10"] = riscv.REG_S10

s2 := append(s1, 3, 5, 7)          // append multiple elements    s2 is []int{0, 0, 2, 3, 5, 7}
s3 := append(s2, s0...)            // append a slice              s3 is []int{0, 0, 2, 3, 5, 7, 0, 0}
s4 := append(s3[3:6], s3[2:]...)   // append overlapping slice    s4 is []int{3, 5, 7, 2, 3, 5, 7, 0, 0}

var t []interface{}
t = append(t, 42, 3.1415, "foo")   //                             t is []interface{}{42, 3.1415, "foo"}

var b []byte