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Results 1 - 3 of 3 for ROLWconst (0.12 sec)
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src/cmd/compile/internal/ssa/_gen/AMD64.rules
(ROLL x (MOV(Q|L)const [c])) => (ROLLconst [int8(c&31)] x) (ROLW x (MOV(Q|L)const [c])) => (ROLWconst [int8(c&15)] x) (ROLB x (MOV(Q|L)const [c])) => (ROLBconst [int8(c&7) ] x) (RORQ x (MOV(Q|L)const [c])) => (ROLQconst [int8((-c)&63)] x) (RORL x (MOV(Q|L)const [c])) => (ROLLconst [int8((-c)&31)] x) (RORW x (MOV(Q|L)const [c])) => (ROLWconst [int8((-c)&15)] x) (RORB x (MOV(Q|L)const [c])) => (ROLBconst [int8((-c)&7) ] x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteAMD64.go
// match: (ROLW x (MOVQconst [c])) // result: (ROLWconst [int8(c&15)] x) for { x := v_0 if v_1.Op != OpAMD64MOVQconst { break } c := auxIntToInt64(v_1.AuxInt) v.reset(OpAMD64ROLWconst) v.AuxInt = int8ToAuxInt(int8(c & 15)) v.AddArg(x) return true } // match: (ROLW x (MOVLconst [c])) // result: (ROLWconst [int8(c&15)] x) for { x := v_0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 712.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ROLWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)