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Results 1 - 7 of 7 for REG_R31 (0.31 sec)
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src/cmd/internal/obj/loong64/a.out.go
REG_R13 REG_R14 REG_R15 REG_R16 REG_R17 REG_R18 REG_R19 REG_R20 REG_R21 REG_R22 REG_R23 REG_R24 REG_R25 REG_R26 REG_R27 REG_R28 REG_R29 REG_R30 REG_R31 REG_F0 // must be a multiple of 32 REG_F1 REG_F2 REG_F3 REG_F4 REG_F5 REG_F6 REG_F7 REG_F8 REG_F9 REG_F10 REG_F11 REG_F12 REG_F13 REG_F14 REG_F15 REG_F16
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 5.7K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/a.out.go
REG_R13 REG_R14 REG_R15 REG_R16 REG_R17 REG_R18 REG_R19 REG_R20 REG_R21 REG_R22 REG_R23 REG_R24 REG_R25 REG_R26 REG_R27 REG_R28 REG_R29 REG_R30 REG_R31 // CR bits. Use Book 1, chapter 2 naming for bits. Keep aligned to 32 REG_CR0LT REG_CR0GT REG_CR0EQ REG_CR0SO REG_CR1LT REG_CR1GT REG_CR1EQ REG_CR1SO REG_CR2LT REG_CR2GT REG_CR2EQ
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 16K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/asm7.go
c.ctxt.Diag("invalid register pair %v\n", p) } case ALDP, ALDPW, ALDPSW: if rl < REG_R0 || REG_R31 < rl || rh < REG_R0 || REG_R31 < rh { c.ctxt.Diag("invalid register pair %v\n", p) } case ASTP, ASTPW: if rl < REG_R0 || REG_R31 < rl || rh < REG_R0 || REG_R31 < rh { c.ctxt.Diag("invalid register pair %v\n", p) } } // other conditional flag bits switch o.scond {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 201.1K bytes - Viewed (0) -
src/cmd/internal/obj/mips/asm0.go
return uint64(uint32(v)) == v } func (c *ctxt0) aclass(a *obj.Addr) int { switch a.Type { case obj.TYPE_NONE: return C_NONE case obj.TYPE_REG: if REG_R0 <= a.Reg && a.Reg <= REG_R31 { return C_REG } if REG_F0 <= a.Reg && a.Reg <= REG_F31 { return C_FREG } if REG_M0 <= a.Reg && a.Reg <= REG_M31 { return C_MREG } if REG_FCR0 <= a.Reg && a.Reg <= REG_FCR31 {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 17:46:09 UTC 2024 - 53.6K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/asm.go
return uint64(uint32(v)) == v } func (c *ctxt0) aclass(a *obj.Addr) int { switch a.Type { case obj.TYPE_NONE: return C_NONE case obj.TYPE_REG: if REG_R0 <= a.Reg && a.Reg <= REG_R31 { return C_REG } if REG_F0 <= a.Reg && a.Reg <= REG_F31 { return C_FREG } if REG_FCSR0 <= a.Reg && a.Reg <= REG_FCSR31 { return C_FCSRREG }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 61.8K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm9.go
func isint32(v int64) bool { return int64(int32(v)) == v } func isuint32(v uint64) bool { return uint64(uint32(v)) == v } func (c *ctxt9) aclassreg(reg int16) int { if REG_R0 <= reg && reg <= REG_R31 { return C_REGP + int(reg&1) } if REG_F0 <= reg && reg <= REG_F31 { return C_FREGP + int(reg&1) } if REG_V0 <= reg && reg <= REG_V31 { return C_VREG }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 13:55:28 UTC 2024 - 156.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
{24, loong64.REG_R25, 20, "R25"}, {25, loong64.REG_R26, 21, "R26"}, {26, loong64.REG_R27, 22, "R27"}, {27, loong64.REG_R28, 23, "R28"}, {28, loong64.REG_R29, 24, "R29"}, {29, loong64.REG_R31, 25, "R31"}, {30, loong64.REG_F0, -1, "F0"}, {31, loong64.REG_F1, -1, "F1"}, {32, loong64.REG_F2, -1, "F2"}, {33, loong64.REG_F3, -1, "F3"}, {34, loong64.REG_F4, -1, "F4"},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)