MOVB	F0, R0             // ERROR "illegal combination"
	MOVH	F0, R0             // ERROR "illegal combination"
	MOVB	R0, F0             // ERROR "illegal combination"
	MOVH	R0, F0             // ERROR "illegal combination"
	MOVB	R0>>0(R1), R2      // ERROR "bad shift"
	MOVB	R0->0(R1), R2      // ERROR "bad shift"
	MOVB	R0@>0(R1), R2      // ERROR "bad shift"
	MOVBS	R0>>0(R1), R2      // ERROR "bad shift"

	ADRP 12(PC), R2    // 02000090

// LDP/STP
	LDP	(R0), (R0, R1)      // 000440a9
	LDP	(R0), (R1, R2)      // 010840a9
	LDP	8(R0), (R1, R2)     // 018840a9
	LDP	-8(R0), (R1, R2)    // 01887fa9
	LDP	11(R0), (R1, R2)    // 1b2c0091610b40a9
	LDP	1024(R0), (R1, R2)  // 1b001091610b40a9
	LDP.W	8(R0), (R1, R2)     // 0188c0a9
	LDP.P	8(R0), (R1, R2)     // 0188c0a8
	LDP	(RSP), (R1, R2)     // e10b40a9

      limiter.acquire(); // #7
    }
    assertEvents(
        "R0.00, R1.38, R1.13, R0.88, R0.63, R0.50, R0.50, R0.50", // #1
        "U0.50", // #2
        "U4.00", // #3
        "R0.00, R1.38, R1.13, R0.88, R0.63, R0.50, R0.50, R0.50", // #4
        "U0.50", // #5
        "U2.00", // #6
        "R0.00, R0.50, R0.50, R0.50, R0.50, R0.50, R0.50, R0.50"); // #7
  }

  public void testWarmUpWithColdFactor() {

      limiter.acquire(); // #7
    }
    assertEvents(
        "R0.00, R1.38, R1.13, R0.88, R0.63, R0.50, R0.50, R0.50", // #1
        "U0.50", // #2
        "U4.00", // #3
        "R0.00, R1.38, R1.13, R0.88, R0.63, R0.50, R0.50, R0.50", // #4
        "U0.50", // #5
        "U2.00", // #6
        "R0.00, R0.50, R0.50, R0.50, R0.50, R0.50, R0.50, R0.50"); // #7
  }

  public void testWarmUpWithColdFactor() {

	CMP R3, R0                      // 7c230000
	CMP R3, R0, CR1                 // CMP R3,CR1,R0   // 7ca30000
	CMPU R3, R4                     // 7c232040
	CMPU R3, R0                     // 7c230040
	CMPU R3, R0, CR2                // CMPU R3,CR2,R0  // 7d230040
	CMPW R3, R4                     // 7c032000
	CMPW R3, R0                     // 7c030000
	CMPW R3, R0, CR3                // CMPW R3,CR3,R0  // 7d830000

	RXSBGT	$17, $8, $16, R9, R10 // eca991081057
	ROSBGT	$9, $24, $11, R11, R0 // ec0b89180b56
	RISBG	$0, $31, $32, R1, R2  // ec21001f2055
	RISBGN	$17, $8, $16, R3, R4  // ec4311081059
	RISBGZ	$9, $24, $11, R5, R6  // ec6509980b55
	RISBGNZ	$0, $31, $32, R7, R8  // ec87009f2059
	RISBHG	$17, $8, $16, R9, R10 // eca91108105d
	RISBLG	$9, $24, $11, R11, R0 // ec0b09180b51
	RISBHGZ	$17, $8, $16, R9, R10 // eca91188105d

	ROTRV	$4, R4			// 84104d00
	SYSCALL				// 00002b00
	BEQ	R4, R5, 1(PC)		// 85040058
	BEQ	R4, 1(PC)		// 80040040
	BEQ	R4, R0, 1(PC)		// 80040040
	BEQ	R0, R4, 1(PC)		// 80040040
	BNE	R4, R5, 1(PC)		// 8504005c
	BNE	R4, 1(PC)		// 80040044
	BNE	R4, R0, 1(PC)		// 80040044
	BNE	R0, R4, 1(PC)		// 80040044
	BLTU	R4, 1(PC)		// 80040068
	MOVF	y+8(FP), F4		// 6440002b
	MOVD	y+8(FP), F4		// 6440802b

		return 10
	}
	if name[0] != 'R' {
		p.errorf("expected g or R0 through R15; found %s", name)
		return 0
	}
	r, ok := p.registerReference(name)
	if !ok {
		return 0
	}
	reg := r - p.arch.Register["R0"]
	if reg < 0 {
		// Could happen for an architecture having other registers prefixed by R
		p.errorf("expected g or R0 through R15; found %s", name)
		return 0
	}
	return uint16(reg)
}

			p.toPatch = append(p.toPatch, Patch{targetAddr, target.Sym.Name})
		} else {
			p.branch(targetAddr, targetProg)
		}
	case target.Type == obj.TYPE_MEM && target.Name == obj.NAME_NONE:
		// JMP 4(R0)
		*targetAddr = *target
		// On the ppc64, 9a encodes BR (CTR) as BR CTR. We do the same.
		if p.arch.Family == sys.PPC64 && target.Offset == 0 {
			targetAddr.Type = obj.TYPE_REG
		}