Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 6 of 6 for F10 (0.05 sec)

  1. src/cmd/asm/internal/asm/testdata/riscv64error.s

    	VFADDVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
    	VFSUBVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
    	VFSUBVF		F10, V2, V4, V3			// ERROR "invalid vector mask register"
    	VFRSUBVF	F10, V2, V4, V3			// ERROR "invalid vector mask register"
    	VFWADDVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
    	VFWADDVF	F10, V2, V4, V3			// ERROR "invalid vector mask register"
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Wed Sep 24 13:21:53 UTC 2025
    - 26.8K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/riscv64.s

    	VFADDVV		V1, V2, V3			// d7912002
    	VFADDVV		V1, V2, V0, V3			// d7912000
    	VFADDVF		F10, V2, V3			// d7512502
    	VFADDVF		F10, V2, V0, V3			// d7512500
    	VFSUBVV		V1, V2, V3			// d791200a
    	VFSUBVV		V1, V2, V0, V3			// d7912008
    	VFSUBVF		F10, V2, V3			// d751250a
    	VFSUBVF		F10, V2, V0, V3			// d7512508
    	VFRSUBVF	F10, V2, V3			// d751259e
    	VFRSUBVF	F10, V2, V0, V3			// d751259c
    
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Thu Nov 13 12:17:37 UTC 2025
    - 73.7K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/riscv64validation.s

    	CLWSP	20(SP), F10				// ERROR "expected integer register in rd position"
    	CLWSP	22(SP), X10				// ERROR "must be a multiple of 4"
    	CLDSP	24(X5), X10				// ERROR "rs2 must be SP/X2"
    	CLDSP	24(SP), X0				// ERROR "cannot use register X0"
    	CLDSP	24(SP), F10				// ERROR "expected integer register in rd position"
    	CLDSP	28(SP), X10				// ERROR "must be a multiple of 8"
    	CFLDSP	32(X5), F10				// ERROR "rs2 must be SP/X2"
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Thu Nov 13 12:17:37 UTC 2025
    - 42.1K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/s390x.s

    	FADDS	F0, F15                // b30a00f0
    	FADD	F1, F14                // b31a00e1
    	FSUBS	F2, F13                // b30b00d2
    	FSUB	F3, F12                // b31b00c3
    	FMULS	F4, F11                // b31700b4
    	FMUL	F5, F10                // b31c00a5
    	FDIVS	F6, F9                 // b30d0096
    	FDIV	F7, F8                 // b31d0087
    	FABS	F1, F2                 // b3100021
    	FSQRTS	F3, F4                 // b3140043
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Wed Jul 30 19:29:15 UTC 2025
    - 22.9K bytes
    - Viewed (0)
  5. tests/migrate_test.go

    	type UserMigrateColumn2 struct {
    		ID  uint
    		F1  string
    		F2  string
    		F3  string
    		F4  string
    		F5  string
    		F6  string
    		F7  string
    		F8  string
    		F9  string
    		F10 string
    		F11 string
    		F12 string
    		F13 string
    		F14 string
    		F15 string
    		F16 string
    		F17 string
    		F18 string
    		F19 string
    		F20 string
    		F21 string
    		F22 string
    		F23 string
    Registered: Sun Dec 28 09:35:17 UTC 2025
    - Last Modified: Wed Aug 20 04:51:17 UTC 2025
    - 65.2K bytes
    - Viewed (0)
  6. src/cmd/asm/internal/asm/testdata/arm64.s

    	FMOVS	F1, 1(R2) // 411000bc
    	FMOVS	F1, 4(R2) // 410400bd
    	FMOVS	F20, (R0) // 140000bd
    	FMOVD	F1, 1(R2) // 411000fc
    	FMOVD	F1, 8(R2) // 410400fd
    	FMOVD	F20, (R2) // 540000fd
    	FMOVQ	F0, 32(R5)// a008803d
    	FMOVQ	F10, 65520(R10) // 4afdbf3d
    	FMOVQ	F11, 64(RSP)    // eb13803d
    	FMOVQ	F11, 8(R20)     // 8b82803c
    	FMOVQ	F11, 4(R20)     // 8b42803c
    
    	MOVB	1(R1), R2 // 22048039
    	MOVH	1(R1), R2 // 22108078
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Mon Nov 10 17:34:13 UTC 2025
    - 96.1K bytes
    - Viewed (0)
Back to top