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Results 1 - 5 of 5 for AFSQRTD (0.14 sec)
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src/cmd/internal/obj/riscv/cpu.go
// 12.3: Double-Precision Load and Store Instructions AFLD AFSD // 12.4: Double-Precision Floating-Point Computational Instructions AFADDD AFSUBD AFMULD AFDIVD AFMIND AFMAXD AFSQRTD AFMADDD AFMSUBD AFNMADDD AFNMSUBD // 12.5: Double-Precision Floating-Point Conversion and Move Instructions AFCVTWD AFCVTLD AFCVTDW AFCVTDL AFCVTWUD AFCVTLUD AFCVTDWU
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.1K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/inst.go
case AFSGNJXQ: return &inst{0x53, 0x2, 0x0, 608, 0x13} case AFSGNJXS: return &inst{0x53, 0x2, 0x0, 512, 0x10} case AFSQ: return &inst{0x27, 0x4, 0x0, 0, 0x0} case AFSQRTD: return &inst{0x53, 0x0, 0x0, 1440, 0x2d} case AFSQRTQ: return &inst{0x53, 0x0, 0x0, 1504, 0x2f} case AFSQRTS: return &inst{0x53, 0x0, 0x0, 1408, 0x2c} case AFSRM:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.9K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
AFSUBD & obj.AMask: rFFFEncoding, AFMULD & obj.AMask: rFFFEncoding, AFDIVD & obj.AMask: rFFFEncoding, AFMIND & obj.AMask: rFFFEncoding, AFMAXD & obj.AMask: rFFFEncoding, AFSQRTD & obj.AMask: rFFFEncoding, AFMADDD & obj.AMask: rFFFFEncoding, AFMSUBD & obj.AMask: rFFFFEncoding, AFNMSUBD & obj.AMask: rFFFFEncoding, AFNMADDD & obj.AMask: rFFFFEncoding,
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/asm7.go
oprangeset(AFNMADDD, t) case AFCVTSD: oprangeset(AFCVTDS, t) oprangeset(AFABSD, t) oprangeset(AFABSS, t) oprangeset(AFNEGD, t) oprangeset(AFNEGS, t) oprangeset(AFSQRTD, t) oprangeset(AFSQRTS, t) oprangeset(AFRINTNS, t) oprangeset(AFRINTND, t) oprangeset(AFRINTPS, t) oprangeset(AFRINTPD, t) oprangeset(AFRINTMS, t) oprangeset(AFRINTMD, t)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 201.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, }, }, { name: "FSQRTD", argLen: 1, asm: arm64.AFSQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 },
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)