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Results 1 - 6 of 6 for AFDIVD (0.25 sec)

  1. src/cmd/internal/obj/riscv/cpu.go

    	AFCLASSS
    
    	// 12.3: Double-Precision Load and Store Instructions
    	AFLD
    	AFSD
    
    	// 12.4: Double-Precision Floating-Point Computational Instructions
    	AFADDD
    	AFSUBD
    	AFMULD
    	AFDIVD
    	AFMIND
    	AFMAXD
    	AFSQRTD
    	AFMADDD
    	AFMSUBD
    	AFNMADDD
    	AFNMSUBD
    
    	// 12.5: Double-Precision Floating-Point Conversion and Move Instructions
    	AFCVTWD
    	AFCVTLD
    	AFCVTDW
    	AFCVTDL
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.1K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/riscv/inst.go

    	case AFCVTWUD:
    		return &inst{0x53, 0x0, 0x1, -991, 0x61}
    	case AFCVTWUQ:
    		return &inst{0x53, 0x0, 0x1, -927, 0x63}
    	case AFCVTWUS:
    		return &inst{0x53, 0x0, 0x1, -1023, 0x60}
    	case AFDIVD:
    		return &inst{0x53, 0x0, 0x0, 416, 0xd}
    	case AFDIVQ:
    		return &inst{0x53, 0x0, 0x0, 480, 0xf}
    	case AFDIVS:
    		return &inst{0x53, 0x0, 0x0, 384, 0xc}
    	case AFENCE:
    		return &inst{0xf, 0x0, 0x0, 0, 0x0}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.9K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/riscv/obj.go

    	// 12.4: Double-Precision Floating-Point Computational Instructions
    	AFADDD & obj.AMask:   rFFFEncoding,
    	AFSUBD & obj.AMask:   rFFFEncoding,
    	AFMULD & obj.AMask:   rFFFEncoding,
    	AFDIVD & obj.AMask:   rFFFEncoding,
    	AFMIND & obj.AMask:   rFFFEncoding,
    	AFMAXD & obj.AMask:   rFFFEncoding,
    	AFSQRTD & obj.AMask:  rFFFEncoding,
    	AFMADDD & obj.AMask:  rFFFFEncoding,
    	AFMSUBD & obj.AMask:  rFFFFEncoding,
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sun Apr 07 03:32:27 UTC 2024
    - 77K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/arm64/asm7.go

    			oprangeset(AFMAXS, t)
    			oprangeset(AFMIND, t)
    			oprangeset(AFMINS, t)
    			oprangeset(AFMAXNMD, t)
    			oprangeset(AFMAXNMS, t)
    			oprangeset(AFMINNMD, t)
    			oprangeset(AFMINNMS, t)
    			oprangeset(AFDIVD, t)
    
    		case AFMSUBD:
    			oprangeset(AFMSUBS, t)
    			oprangeset(AFMADDS, t)
    			oprangeset(AFMADDD, t)
    			oprangeset(AFNMSUBS, t)
    			oprangeset(AFNMSUBD, t)
    			oprangeset(AFNMADDS, t)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 201.1K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/x86/asm6.go

    	{AFDIVDP, ycompp, Px, opBytes{0xde, 07}},
    	{AFDIVW, yfmvx, Px, opBytes{0xde, 06}},
    	{AFDIVL, yfmvx, Px, opBytes{0xda, 06}},
    	{AFDIVF, yfmvx, Px, opBytes{0xd8, 06}},
    	{AFDIVD, yfadd, Px, opBytes{0xdc, 06, 0xd8, 06, 0xdc, 07}},
    	{AFDIVRDP, ycompp, Px, opBytes{0xde, 06}},
    	{AFDIVRW, yfmvx, Px, opBytes{0xde, 07}},
    	{AFDIVRL, yfmvx, Px, opBytes{0xda, 07}},
    	{AFDIVRF, yfmvx, Px, opBytes{0xd8, 07}},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 146.9K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/opGen.go

    			},
    		},
    	},
    	{
    		name:   "FDIVD",
    		argLen: 2,
    		asm:    arm64.AFDIVD,
    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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