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Results 1 - 3 of 3 for ADDUW (0.04 sec)
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src/cmd/internal/obj/riscv/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 2.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
// 12.6: Double-Precision Floating-Point Classify Instruction FCLASSD F0, X5 // d31200e2 // RISC-V Bit-Manipulation ISA-extensions (1.0) // 1.1: Address Generation Instructions (Zba) ADDUW X10, X11, X12 // 3b86a508 ADDUW X10, X11 // bb85a508 SH1ADD X11, X12, X13 // b326b620 SH1ADD X11, X12 // 3326b620 SH1ADDUW X12, X13, X14 // 3ba7c620 SH1ADDUW X12, X13 // bba6c620 SH2ADD X13, X14, X15 // b347d720
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 22 04:42:21 UTC 2024 - 16.7K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
} ins2 := &instruction{as: ASRAI, rd: ins.rd, rs1: ins.rd, imm: ins.imm} inss = append(inss, ins2) } case AMOVHU, AMOVWU: if buildcfg.GORISCV64 >= 22 { // Use ZEXTH or ADDUW to extend. ins.as, ins.rs1, ins.rs2, ins.imm = AZEXTH, uint32(p.From.Reg), obj.REG_NONE, 0 if p.As == AMOVWU { ins.as, ins.rs2 = AADDUW, REG_ZERO } } else {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0)