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Results 1 - 4 of 4 for ADDQconst (0.17 sec)

  1. src/cmd/compile/internal/ssa/_gen/AMD64.rules

    (SUBQconst [c] x) && c != -(1<<31) => (ADDQconst [-c] x)
    (SUBLconst [c] x) => (ADDLconst [-c] x)
    
    // generic constant folding
    // TODO: more of this
    (ADDQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)+d])
    (ADDLconst [c] (MOVLconst [d])) => (MOVLconst [c+d])
    (ADDQconst [c] (ADDQconst [d] x)) && is32Bit(int64(c)+int64(d)) => (ADDQconst [c+d] x)
    (ADDLconst [c] (ADDLconst [d] x)) => (ADDLconst [c+d] x)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 93.9K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/rewriteAMD64.go

    			break
    		}
    		d := auxIntToInt64(v_0.AuxInt)
    		v.reset(OpAMD64MOVQconst)
    		v.AuxInt = int64ToAuxInt(int64(c) + d)
    		return true
    	}
    	// match: (ADDQconst [c] (ADDQconst [d] x))
    	// cond: is32Bit(int64(c)+int64(d))
    	// result: (ADDQconst [c+d] x)
    	for {
    		c := auxIntToInt32(v.AuxInt)
    		if v_0.Op != OpAMD64ADDQconst {
    			break
    		}
    		d := auxIntToInt32(v_0.AuxInt)
    		x := v_0.Args[0]
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 712.7K bytes
    - Viewed (0)
  3. test/codegen/comparisons.go

    	// amd64:-`CMPQ\tcommand-line-arguments[.+_a-z0-9]+\(SP\), [A-Z]`
    	// amd64:`CALL`
    	return s1 == s2
    }
    
    // -------------- //
    //    Ordering    //
    // -------------- //
    
    // Test that LEAQ/ADDQconst are folded into SETx ops
    
    var r bool
    
    func CmpFold(x uint32) {
    	// amd64:`SETHI\t.*\(SB\)`
    	r = x > 4
    }
    
    // Test that direct comparisons with memory are generated when
    // possible
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Apr 19 16:31:02 UTC 2024
    - 15.2K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/opGen.go

    			},
    			outputs: []outputInfo{
    				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
    			},
    		},
    	},
    	{
    		name:         "ADDQconst",
    		auxType:      auxInt32,
    		argLen:       1,
    		clobberFlags: true,
    		asm:          x86.AADDQ,
    		reg: regInfo{
    			inputs: []inputInfo{
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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