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Results 1 - 4 of 4 for z2 (0.09 sec)
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src/test/java/org/codelibs/fess/dict/synonym/SynonymFileTest.java
assertEquals("Z2", itemList2.get(5).getOutputs()[1]); final SynonymItem synonymItem2 = new SynonymItem(0, new String[] {"z1", "z2" }, new String[] { "z1", "z2" }); synonymFile.insert(synonymItem2); final PagingList<SynonymItem> itemList3 = synonymFile.selectList(0, 20); assertEquals(7, itemList3.size()); assertEquals("z1", itemList3.get(6).getInputs()[0]);
Registered: Thu Sep 04 12:52:25 UTC 2025 - Last Modified: Sat Mar 15 06:53:53 UTC 2025 - 9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
VADDPD.Z X30, X1, K7, X0 // 6291f58f58c6 VMAXPD.Z (AX), Z2, K1, Z1 // 62f1edc95f08 // EVEX: embedded rounding. VADDPD.RU_SAE Z3, Z2, K1, Z1 // 62f1ed5958cb VADDPD.RD_SAE Z3, Z2, K1, Z1 // 62f1ed3958cb VADDPD.RZ_SAE Z3, Z2, K1, Z1 // 62f1ed7958cb VADDPD.RN_SAE Z3, Z2, K1, Z1 // 62f1ed1958cb VADDPD.RU_SAE.Z Z3, Z2, K1, Z1 // 62f1edd958cb VADDPD.RD_SAE.Z Z3, Z2, K1, Z1 // 62f1edb958cb
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Thu Feb 20 11:20:03 UTC 2025 - 57.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64error.s
// "K0 can't be used for write mask" VADDPD X0, X1, K0, X2 // ERROR "invalid instruction" VADDPD Y0, Y1, K0, Y2 // ERROR "invalid instruction" VADDPD Z0, Z1, K0, Z2 // ERROR "invalid instruction" // VEX-encoded VSIB can't use High-16 registers as index (unlike EVEX). // TODO(quasilyte): improve error message (#21860). VPGATHERQQ X2, (BP)(X20*2), X3 // ERROR "invalid instruction"
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Jun 14 00:03:57 UTC 2023 - 8.9K bytes - Viewed (0) -
lib/fips140/v1.0.0.zip
* Y3 = R*Y3 * Y3 = Y3-T2 << store-out Y3 result reg // X=Z1; Y=Z1; MUL; T- // T1 = Z1*Z1 // X- ; Y=T ; MUL; R=T // R = Z1*T1 // X=X2; Y- ; MUL; H=T // H = X2*T1 // X=Z2; Y=Z2; MUL; T- // T2 = Z2*Z2 // X- ; Y=T ; MUL; S1=T // S1 = Z2*T2 // X=X1; Y- ; MUL; U1=T // U1 = X1*T2 // SUB(H<H-T) // H = H-U1 // X=Z1; Y=Z2; MUL; T- // Z3 = Z1*Z2 // X=T ; Y=H ; MUL; Z3:=T// Z3 = Z3*H << store-out Z3 result reg.. could override Z1, if slices have same backing array // X=Y1; Y=S1; MUL; S1=T // S1 = Y1*S1 // X=Y2;...
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Jan 29 15:10:35 UTC 2025 - 635K bytes - Viewed (0)