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Results 1 - 10 of 29 for rreg (0.05 sec)
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src/cmd/asm/internal/asm/testdata/mips64.s
// LFADD freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } ADDD F1, F2 // LFADD freg ',' freg ',' freg // { // outcode(int($1), &$2, int($4.Reg), &$6); // } ADDD F1, F2, F3 // LFCMP freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } CMPEQD F1, F2 // // WORD // WORD $1 // 00000001 NOOP // 00000000 SYNC // 0000000f //
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
// } ADD $4, R1 // LMUL rreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MUL R1, R2 // LSHW rreg ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // } SLL R1, R2, R3 // LSHW rreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } SLL R1, R2 // LSHW imm ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // }
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 6.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
// MULL r1,r2,(hi,lo) // // LTYPEM cond reg ',' reg ',' regreg // { // outcode($1, $2, &$3, int32($5.Reg), &$7); // } MULL R1, R2, (R3,R4) // // MULA r1,r2,r3,r4: (r1*r2+r3) & 0xffffffff . r4 // MULAW{T,B} r1,r2,r3,r4 // // LTYPEN cond reg ',' reg ',' reg ',' spreg // { // $7.Type = obj.TYPE_REGREG2; // $7.Offset = int64($9); // outcode($1, $2, &$3, int32($5.Reg), &$7); // } MULAWT R1, R2, R3, R4
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0) -
src/cmd/asm/internal/arch/loong64.go
} if isIndex { arng_type, ok = loong64ElemExtMap[ext] if !ok { return errors.New("Loong64 extension: invalid LSX/LASX arrangement type: " + ext) } a.Reg = loong64.REG_ELEM a.Reg += ((reg & loong64.EXT_REG_MASK) << loong64.EXT_REG_SHIFT) a.Reg += ((arng_type & loong64.EXT_TYPE_MASK) << loong64.EXT_TYPE_SHIFT)
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Tue Aug 05 17:31:25 UTC 2025 - 3.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/parse.go
// Expect (SB), (FP), (PC), or (SP) p.get('(') reg := p.get(scanner.Ident).String() p.get(')') p.setPseudoRegister(a, reg, isStatic, prefix) } // setPseudoRegister sets the NAME field of addr for a pseudo-register reference such as (SB). func (p *Parser) setPseudoRegister(addr *obj.Addr, reg string, isStatic bool, prefix rune) { if addr.Reg != 0 { p.errorf("internal error: reg %s already set in pseudo", reg) } switch reg {
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Fri Feb 14 15:13:11 UTC 2025 - 37.3K bytes - Viewed (0) -
cmd/bucket-lifecycle.go
func putRestoreOpts(bucket, object string, rreq *RestoreObjectRequest, objInfo ObjectInfo) (putOpts ObjectOptions) { meta := make(map[string]string) sc := rreq.OutputLocation.S3.StorageClass if sc == "" { sc = objInfo.StorageClass } meta[strings.ToLower(xhttp.AmzStorageClass)] = sc if rreq.Type == SelectRestoreRequest { for _, v := range rreq.OutputLocation.S3.UserMetadata {
Registered: Sun Sep 07 19:28:11 UTC 2025 - Last Modified: Fri Aug 29 02:39:48 UTC 2025 - 33.7K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm64.go
} } else if reg <= arm64.REG_V31 && reg >= arm64.REG_V0 { switch ext { case "B8": if isIndex { return errors.New("invalid register extension") } a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8B & 15) << 5) case "B16": if isIndex { return errors.New("invalid register extension") } a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_16B & 15) << 5)
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Fri Feb 14 15:13:11 UTC 2025 - 10.3K bytes - Viewed (0) -
src/test/java/jcifs/internal/witness/MockWitnessService.java
// Count how many registrations this affects int affectedRegistrations = 0; for (MockRegistration reg : registrations.values()) { if (reg.shareName.equalsIgnoreCase(resourceName) || reg.serverAddress.equals(resourceName)) { affectedRegistrations++; } }
Registered: Sun Sep 07 00:10:21 UTC 2025 - Last Modified: Sat Aug 23 09:06:40 UTC 2025 - 8.2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/asm.go
// the CR bit. prog.Reg = a[1].Reg if a[1].Type != obj.TYPE_REG { // The CR bit is represented as a constant 0-31. Convert it to a Reg. c := p.getConstant(prog, op, &a[1]) reg, success := ppc64.ConstantToCRbit(c) if !success { p.errorf("invalid CR bit register number %d", c) } prog.Reg = reg } break }
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Tue Aug 05 17:31:25 UTC 2025 - 26.2K bytes - Viewed (0) -
src/test/java/jcifs/internal/witness/WitnessClientTest.java
WitnessRegisterResponse mockResponse = mock(WitnessRegisterResponse.class); lenient().when(mockResponse.isSuccess()).thenReturn(true); lenient().when(mockResponse.getRegistrationId()).thenReturn("test-reg-123"); WitnessRpcClient mockRpc = mock(WitnessRpcClient.class); lenient().when(mockRpc.register(any(WitnessRegisterRequest.class))).thenReturn(mockResponse);
Registered: Sun Sep 07 00:10:21 UTC 2025 - Last Modified: Sat Aug 23 09:06:40 UTC 2025 - 9.8K bytes - Viewed (0)