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src/cmd/asm/internal/asm/testdata/mips.s
// } ADD $4, R1 // LMUL rreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MUL R1, R2 // LSHW rreg ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // } SLL R1, R2, R3 // LSHW rreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } SLL R1, R2 // LSHW imm ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // }Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 6.7K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
// LFADD freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } ADDD F1, F2 // LFADD freg ',' freg ',' freg // { // outcode(int($1), &$2, int($4.Reg), &$6); // } ADDD F1, F2, F3 // LFCMP freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } CMPEQD F1, F2 // // WORD // WORD $1 // 00000001 NOOP // 00000000 SYNC // 0000000f //Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 12.4K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/arm.s
// MULL r1,r2,(hi,lo) // // LTYPEM cond reg ',' reg ',' regreg // { // outcode($1, $2, &$3, int32($5.Reg), &$7); // } MULL R1, R2, (R3,R4) // // MULA r1,r2,r3,r4: (r1*r2+r3) & 0xffffffff . r4 // MULAW{T,B} r1,r2,r3,r4 // // LTYPEN cond reg ',' reg ',' reg ',' spreg // { // $7.Type = obj.TYPE_REGREG2; // $7.Offset = int64($9); // outcode($1, $2, &$3, int32($5.Reg), &$7); // } MULAWT R1, R2, R3, R4Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Fri Dec 15 20:51:01 GMT 2023 - 69K bytes - Click Count (0) -
src/cmd/asm/internal/arch/loong64.go
func Loong64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, isIndex bool) error { var ok bool var arngType int16 var simdType int16 var simdReg int16 switch { case reg >= loong64.REG_V0 && reg <= loong64.REG_V31: simdType = loong64.LSX simdReg = reg - loong64.REG_V0 case reg >= loong64.REG_X0 && reg <= loong64.REG_X31: simdType = loong64.LASX simdReg = reg - loong64.REG_X0 default:
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Sat Feb 14 15:17:33 GMT 2026 - 3.9K bytes - Click Count (0) -
src/test/resources/jcifs/smb1/util/mime.map
audio/x-mpegurl mp3 # MP3 Sound File audio/mpeg3 mp3 # MP3 Sound File audio/x-mpeg-3 mp3 # MP3 Sound File audio/mpeg mp2 mpa mpg mpga # MP2 Sound File audio/x-mpeg mp2 # MP2 Sound File chemical/x-pdb pdb # PDB Chemistry Model File
Created: Sun Apr 05 00:10:12 GMT 2026 - Last Modified: Thu Aug 14 05:31:44 GMT 2025 - 5.9K bytes - Click Count (0) -
src/cmd/asm/internal/asm/asm.go
// the CR bit. prog.Reg = a[1].Reg if a[1].Type != obj.TYPE_REG { // The CR bit is represented as a constant 0-31. Convert it to a Reg. c := p.getConstant(prog, op, &a[1]) reg, success := ppc64.ConstantToCRbit(c) if !success { p.errorf("invalid CR bit register number %d", c) } prog.Reg = reg } break }Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Fri Mar 20 17:02:17 GMT 2026 - 27.5K bytes - Click Count (0) -
src/cmd/asm/internal/asm/parse.go
// Expect (SB), (FP), (PC), or (SP) p.get('(') reg := p.get(scanner.Ident).String() p.get(')') p.setPseudoRegister(a, reg, isStatic, prefix) } // setPseudoRegister sets the NAME field of addr for a pseudo-register reference such as (SB). func (p *Parser) setPseudoRegister(addr *obj.Addr, reg string, isStatic bool, prefix rune) { if addr.Reg != 0 { p.errorf("internal error: reg %s already set in pseudo", reg) } switch reg {
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Tue Feb 17 19:57:47 GMT 2026 - 37.3K bytes - Click Count (0) -
src/cmd/asm/internal/arch/arm64.go
} // ARM64RegisterShift constructs an ARM64 register with shift operation. func ARM64RegisterShift(reg, op, count int16) (int64, error) { // the base register of shift operations must be general register. if reg > arm64.REG_R31 || reg < arm64.REG_R0 { return 0, errors.New("invalid register for shift operation") } return int64(reg&31)<<16 | int64(op)<<22 | int64(uint16(count)), nil }
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Fri Mar 20 17:02:17 GMT 2026 - 6K bytes - Click Count (0) -
src/cmd/asm/internal/lex/lex_test.go
"\tb\\", "\tc", "before", "A(1, 2, 3)", "after", ), "before.\n.1.\n.2.\n.3.\n.after.\n", }, { "LOAD macro", lines( "#define LOAD(off, reg) \\", "\tMOVBLZX (off*4)(R12), reg \\", "\tADDB reg, DX", "", "LOAD(8, AX)", ), "\n.\n.MOVBLZX.(.8.*.4.).(.R12.).,.AX.\n.ADDB.AX.,.DX.\n", }, { "nested multiline macro", lines(
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Tue Aug 29 07:48:38 GMT 2023 - 5.8K bytes - Click Count (0) -
src/main/resources/fess_indices/fess/hu/stopwords.txt
kellett keresztül keressünk ki kívül között közül legalább lehet lehetett legyen lenne lenni lesz lett maga magát majd majd már más másik meg még mellett mert mely melyek mi mit míg miért milyen mikor minden mindent mindenki mindig mint mintha mivel most nagy nagyobb nagyon ne
Created: Tue Mar 31 13:07:34 GMT 2026 - Last Modified: Mon Nov 27 12:59:36 GMT 2023 - 1.3K bytes - Click Count (0)