ANDL    $0x7FF, BX
	SUBL    $0x3FE, BX
	XORPS   X1, X1 // break dependency for CVTSL2SD
	CVTSL2SD BX, X1 // x1= k, x2= f1
	// if f1 < math.Sqrt2/2 { k -= 1; f1 *= 2 }
	MOVSD   $HSqrt2, X0 // x0= 0.7071, x1= k, x2= f1
	CMPSD   X2, X0, 5 // cmpnlt; x0= 0 or ^0, x1= k, x2 = f1
	MOVSD   $1.0, X3 // x0= 0 or ^0, x1= k, x2 = f1, x3= 1
	ANDPD   X0, X3 // x0= 0 or ^0, x1= k, x2 = f1, x3= 0 or 1
	SUBSD   X3, X1 // x0= 0 or ^0, x1= k, x2 = f1, x3= 0 or 1

	"CMOVWLS",
	"CMOVWLT",
	"CMOVWMI",
	"CMOVWNE",
	"CMOVWOC",
	"CMOVWOS",
	"CMOVWPC",
	"CMOVWPL",
	"CMOVWPS",
	"CMPB",
	"CMPL",
	"CMPPD",
	"CMPPS",
	"CMPQ",
	"CMPSB",
	"CMPSD",
	"CMPSL",
	"CMPSQ",
	"CMPSS",
	"CMPSW",
	"CMPW",
	"CMPXCHG16B",
	"CMPXCHG8B",
	"CMPXCHGB",
	"CMPXCHGL",
	"CMPXCHGQ",
	"CMPXCHGW",
	"COMISD",
	"COMISS",
	"CPUID",
	"CQO",

	TR2:  "%tr2",
	TR3:  "%tr3",
	TR4:  "%tr4",
	TR5:  "%tr5",
	TR6:  "%tr6",
	TR7:  "%tr7",
}

var gnuOp = map[Op]string{
	CBW:       "cbtw",
	CDQ:       "cltd",
	CMPSD:     "cmpsl",
	CMPSD_XMM: "cmpsd",
	CWD:       "cwtd",
	CWDE:      "cwtl",
	CQO:       "cqto",
	INSD:      "insl",
	IRET:      "iretw",
	IRETD:     "iret",
	IRETQ:     "iretq",
	LODSB:     "lods",

		inst.Args[0] = Mem{Segment: ES, Base: baseRegForBits(addrMode) + DI - AX}
		inst.Args[1] = Mem{Segment: defaultSeg(), Base: baseRegForBits(addrMode) + SI - AX}
		usedAddrSize = true

	case CMPSB, CMPSW, CMPSD, CMPSQ:
		inst.Args[0] = Mem{Segment: defaultSeg(), Base: baseRegForBits(addrMode) + SI - AX}
		inst.Args[1] = Mem{Segment: ES, Base: baseRegForBits(addrMode) + DI - AX}
		usedAddrSize = true

	CMOVP:           "CMOVP",
	CMOVS:           "CMOVS",
	CMP:             "CMP",
	CMPPD:           "CMPPD",
	CMPPS:           "CMPPS",
	CMPSB:           "CMPSB",
	CMPSD:           "CMPSD",
	CMPSD_XMM:       "CMPSD_XMM",
	CMPSQ:           "CMPSQ",
	CMPSS:           "CMPSS",
	CMPSW:           "CMPSW",
	CMPXCHG:         "CMPXCHG",
	CMPXCHG16B:      "CMPXCHG16B",
	CMPXCHG8B:       "CMPXCHG8B",

	CMPSD X2, X11, $7                       // f2440fc2da07
	CMPSD X11, X11, $7                      // f2450fc2db07
	CMPSQ                                   // 48a7
	CMPSS (BX), X2, $7                      // f30fc21307
	CMPSS (R11), X2, $7                     // f3410fc21307
	CMPSS X2, X2, $7                        // f30fc2d207
	CMPSS X11, X2, $7                       // f3410fc2d307

	case STB, STBU,
		STH, STHU,
		STW, STWU,
		STD, STDU,
		STFD, STFDU,
		STFS, STFSU,
		STQ, HASHST, HASHSTP:
		return op + " " + strings.Join(args, ",")

	case FCMPU, FCMPO, CMPD, CMPDI, CMPLD, CMPLDI, CMPW, CMPWI, CMPLW, CMPLWI:
		crf := int(inst.Args[0].(CondReg) - CR0)
		cmpstr := op + " " + args[1] + "," + args[2]
		if crf != 0 { // print CRx as the final operand if not implied (i.e BF != 0)

	MOVBU	2(X12), X18
	MOVBU	3(X12), X20
	MOVBU	4(X12), X22
	MOVBU	5(X12), X24
	MOVBU	6(X12), X28
	MOVBU	7(X12), X30
	BNE	X8, X9, cmp1a
	BNE	X15, X16, cmp1b
	BNE	X17, X18, cmp1c
	BNE	X19, X20, cmp1d
	BNE	X21, X22, cmp1e
	BNE	X23, X24, cmp1f
	BNE	X25, X28, cmp1g
	BNE	X29, X30, cmp1h
	ADD	$8, X10
	ADD	$8, X12
	SUB	$8, X5
	BGE	X5, X6, compare8_unaligned
	BEQZ	X5, cmp_len

check4_unaligned:

	{VSQRT_EQ_F32, []int{1, 0}, "VSQRT", "SQRTF"},
	{VSQRT_EQ_F64, []int{1, 0}, "VSQRT", "SQRTD"},
	{VCMP_EQ_F32, []int{1, 0}, "VCMP", "CMPF"},
	{VCMP_EQ_F64, []int{1, 0}, "VCMP", "CMPD"},
	{VCMP_E_EQ_F32, []int{1, 0}, "VCMP.E", "CMPF"},
	{VCMP_E_EQ_F64, []int{1, 0}, "VCMP.E", "CMPD"},
	{VLDR_EQ, []int{1}, "VLDR", "MOV"},
	{VSTR_EQ, []int{1}, "VSTR", "MOV"},
	{VMOV_EQ_F32, []int{1, 0}, "VMOV", "MOVF"},
	{VMOV_EQ_F64, []int{1, 0}, "VMOV", "MOVD"},

	ACMOVWHI
	ACMOVWLE
	ACMOVWLS
	ACMOVWLT
	ACMOVWMI
	ACMOVWNE
	ACMOVWOC
	ACMOVWOS
	ACMOVWPC
	ACMOVWPL
	ACMOVWPS
	ACMPB
	ACMPL
	ACMPPD
	ACMPPS
	ACMPQ
	ACMPSB
	ACMPSD
	ACMPSL
	ACMPSQ
	ACMPSS
	ACMPSW
	ACMPW
	ACMPXCHG16B
	ACMPXCHG8B
	ACMPXCHGB
	ACMPXCHGL
	ACMPXCHGQ
	ACMPXCHGW
	ACOMISD
	ACOMISS
	ACPUID
	ACQO
	ACRC32B
	ACRC32L