synonymFile.insert(synonymItem1);
         final PagingList<SynonymItem> itemList2 = synonymFile.selectList(0, 20);
         assertEquals(6, itemList2.size());
         assertEquals("z1", itemList2.get(5).getInputs()[0]);
         assertEquals("z2", itemList2.get(5).getInputs()[1]);
         assertEquals("Z1", itemList2.get(5).getOutputs()[0]);

	ZASR Z1.S, Z26.S, P14.M, Z7.D                     // ERROR "illegal combination from SVE"
	ZASRR Z1.S, Z26.S, P14.M, Z7.D                    // ERROR "illegal combination from SVE"
	ZBCAX Z1.S, Z26.S, Z11.B, Z7.D                    // ERROR "illegal combination from SVE"
	ZBDEP Z1.S, Z26.S, Z11.B                          // ERROR "illegal combination from SVE"

	VADDPD.Z X30, X1, K7, X0  // 6291f58f58c6
	VMAXPD.Z (AX), Z2, K1, Z1 // 62f1edc95f08
	// EVEX: embedded rounding.
	VADDPD.RU_SAE Z3, Z2, K1, Z1   // 62f1ed5958cb
	VADDPD.RD_SAE Z3, Z2, K1, Z1   // 62f1ed3958cb
	VADDPD.RZ_SAE Z3, Z2, K1, Z1   // 62f1ed7958cb
	VADDPD.RN_SAE Z3, Z2, K1, Z1   // 62f1ed1958cb
	VADDPD.RU_SAE.Z Z3, Z2, K1, Z1 // 62f1edd958cb
	VADDPD.RD_SAE.Z Z3, Z2, K1, Z1 // 62f1edb958cb
	VADDPD.RZ_SAE.Z Z3, Z2, K1, Z1 // 62f1edf958cb

	UMWAIT (BX)                      // ERROR "invalid instruction"
	// .Z instructions
	VMOVDQA32.Z Z0, Z1               // ERROR "mask register must be specified for .Z instructions"
	VMOVDQA32.Z Z0, K0, Z1           // ERROR "invalid instruction"
	VMOVDQA32.Z Z0, K1, Z1           // ok

	RDPID (BX)			 // ERROR "invalid instruction"

	CMPL runtime·writeBarrier(SB), $0
	SHLXQ AX, CX, R15
	ADDQ $1, R15
	RET

// Ensure from3 get GOT-rewritten without errors.
TEXT ·a35(SB), 0, $0-0
	VGF2P8AFFINEQB	$0, runtime·writeBarrier(SB), Z1, Z1

        responseDataMap.put("z", "Z0");
        responseDataMap.put("z.overwrite", "Z1");

        indexUpdateCallback.mergeResponseData(dataMap, responseDataMap);

        assertFalse(dataMap.containsKey("z.overwrite"));
        assertEquals(1, dataMap.size());
        assertEquals("Z1", dataMap.get("z"));
    }

Y3 = U1-X3 * Y3 = R*Y3 * Y3 = Y3-T2 << store-out Y3 result reg // X=Z1; Y=Z1; MUL; T- // T1 = Z1*Z1 // X- ; Y=T ; MUL; R=T // R = Z1*T1 // X=X2; Y- ; MUL; H=T // H = X2*T1 // X=Z2; Y=Z2; MUL; T- // T2 = Z2*Z2 // X- ; Y=T ; MUL; S1=T // S1 = Z2*T2 // X=X1; Y- ; MUL; U1=T // U1 = X1*T2 // SUB(H<H-T) // H = H-U1 // X=Z1; Y=Z2; MUL; T- // Z3 = Z1*Z2 // X=T ; Y=H ; MUL; Z3:=T// Z3 = Z3*H << store-out Z3 result reg.. could override Z1, if slices have same backing array // X=Y1; Y=S1; MUL; S1=T // S1 =...

Y3 = U1-X3 * Y3 = R*Y3 * Y3 = Y3-T2 << store-out Y3 result reg // X=Z1; Y=Z1; MUL; T- // T1 = Z1*Z1 // X- ; Y=T ; MUL; R=T // R = Z1*T1 // X=X2; Y- ; MUL; H=T // H = X2*T1 // X=Z2; Y=Z2; MUL; T- // T2 = Z2*Z2 // X- ; Y=T ; MUL; S1=T // S1 = Z2*T2 // X=X1; Y- ; MUL; U1=T // U1 = X1*T2 // SUB(H<H-T) // H = H-U1 // X=Z1; Y=Z2; MUL; T- // Z3 = Z1*Z2 // X=T ; Y=H ; MUL; Z3:=T// Z3 = Z3*H << store-out Z3 result reg.. could override Z1, if slices have same backing array // X=Y1; Y=S1; MUL; S1=T // S1 =...

	ZFDOT Z7.B, Z6.B, Z23.S                           // d7846764
	ZFDOT Z7.B, Z6.B, Z23.H                           // d7842764
	ZFDOT Z7.H, Z6.H, Z23.S                           // d7802764
	ZFEXPA Z1.S, Z26.S                                // 3ab8a004
	ZFLOGB Z7.D, P4.M, Z13.D                          // edb01e65
	ZFLOGB Z7.D, P4.Z, Z13.D                          // edf01e64