FABSD F0, F14                              // 0ec0601e
	//TODO FACGE F25, F16, F0                  // 00ee797e
	//TODO VFACGE V11.S2, V15.S2, V9.S2        // e9ed2b2e
	//TODO FACGT F20, F16, F27                 // 1beef47e
	//TODO VFACGT V15.S4, V25.S4, V22.S4       // 36efaf6e
	//TODO VFADD V21.D2, V10.D2, V21.D2        // 55d5754e
	FADDS F12, F2, F10                         // 4a282c1e

	VLD1R.P	(R15)(R1), [V15.H4]                             // efc5c10d
	VLD2R	(R15), [V15.H4, V16.H4]                         // efc5600d
	VLD2R.P	16(R0), [V0.D2, V1.D2]                          // 00ccff4d
	VLD2R.P	(R0)(R5), [V31.D1, V0.D1]                       // 1fcce50d
	VLD3R	(RSP), [V31.S2, V0.S2, V1.S2]                   // ffeb400d
	VLD3R.P	6(R15), [V15.H4, V16.H4, V17.H4]                // efe5df0d

	VST	V1, (R15)               // e710f000000e
	VL	(R15), V31              // e7f0f0000806
	VST	V31, (R15)              // e7f0f000080e
	VESLB	$5, V14                 // e7ee00050030
	VESRAG	$0, V15, V16            // e70f0000383a
	VLM	(R15), V8, V23          // e787f0000436
	VSTM	V8, V23, (R15)          // e787f000043e
	VONE	V1                      // e710ffff0044
	VZERO	V16                     // e70000000844

	{"V4", "V4"},
	{"V5", "V5"},
	{"V6", "V6"},
	{"V7", "V7"},
	{"V8", "V8"},
	{"V9", "V9"},
	{"V10", "V10"},
	{"V11", "V11"},
	{"V12", "V12"},
	{"V13", "V13"},
	{"V14", "V14"},
	{"V15", "V15"},
	{"V16", "V16"},
	{"V17", "V17"},
	{"V18", "V18"},
	{"V19", "V19"},
	{"V20", "V20"},
	{"V21", "V21"},
	{"V22", "V22"},
	{"V23", "V23"},
	{"V24", "V24"},
	{"V25", "V25"},

	MRS	PMSWINC_EL0, R3                                  // ERROR "system register is not readable"
	MRS	OSLAR_EL1, R3                                    // ERROR "system register is not readable"
	VLD3R.P	24(R15), [V15.H4,V16.H4,V17.H4]                  // ERROR "invalid post-increment offset"
	VBIT	V1.H4, V12.H4, V3.H4                             // ERROR "invalid arrangement"