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Results 1 - 10 of 16 for AX (0.03 sec)
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src/cmd/asm/internal/asm/testdata/amd64error.s
MOVQ 2147483647+1(AX), AX // ERROR "offset too large" MOVQ 3395469782(R10), R8 // ERROR "offset too large" LEAQ 3395469782(AX), AX // ERROR "offset too large" ADDQ 3395469782(AX), AX // ERROR "offset too large" ADDL 3395469782(AX), AX // ERROR "offset too large" ADDW 3395469782(AX), AX // ERROR "offset too large" LEAQ 433954697820(AX), AX // ERROR "offset too large"
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Wed Jun 14 00:03:57 UTC 2023 - 8.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/386enc.s
MOVQ (AX), M0 // 0f6f00 MOVQ M0, 8(SP) // 0f7f442408 MOVQ 8(SP), M0 // 0f6f442408 MOVQ M0, (AX) // 0f7f00 MOVQ M0, (BX) // 0f7f03 // On non-64bit arch, Go asm allowed uint32 offsets instead of int32. // These tests check that property for backwards-compatibility. MOVL 2147483648(AX), AX // 8b8000000080 MOVL -2147483648(AX), AX // 8b8000000080 ADDL 2147483648(AX), AX // 038000000080
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Tue Apr 11 18:32:50 UTC 2023 - 1.2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
VADDPD X30, X29, X28 // 6201950058e6 VADDPD (AX), X29, X0 // 62f195005800 VADDPD (AX), X1, X28 // 6261f5085820 VADDPD (AX), X29, X28 // 626195005820 VADDPD (AX), X29, X10 // 627195005810 VADDPD (AX), X10, X28 // 6261ad085820 VADDPD (CX)(AX*1), X29, X0 // 62f19500580401 VADDPD (CX)(AX*1), X1, X28 // 6261f508582401 VADDPD (CX)(AX*1), X29, X28 // 62619500582401
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Feb 20 11:20:03 UTC 2025 - 57.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64dynlinkerror.s
RET TEXT ·a23(SB), 0, $0-0 CMPL runtime·writeBarrier(SB), $0 LEAQ (AX)(CX*1), R15 RET TEXT ·a24(SB), 0, $0-0 CMPL runtime·writeBarrier(SB), $0 LEAQ (R15)(AX*1), AX // ERROR "when dynamic linking, R15 is clobbered by a global variable access and is used here" RET TEXT ·a25(SB), 0, $0-0 CMPL runtime·writeBarrier(SB), $0
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 20 19:05:03 UTC 2025 - 4.9K bytes - Viewed (0) -
lib/fips140/v1.0.0-c2097c7c.zip
JB Ldec128 MOVUPS (AX), X1 AESDEC X1, X0 MOVUPS 16(AX), X1 AESDEC X1, X0 ADDQ $0x20, AX Ldec192: MOVUPS (AX), X1 AESDEC X1, X0 MOVUPS 16(AX), X1 AESDEC X1, X0 ADDQ $0x20, AX Ldec128: MOVUPS (AX), X1 AESDEC X1, X0 MOVUPS 16(AX), X1 AESDEC X1, X0 MOVUPS 32(AX), X1 AESDEC X1, X0 MOVUPS 48(AX), X1 AESDEC X1, X0 MOVUPS 64(AX), X1 AESDEC X1, X0 MOVUPS 80(AX), X1 AESDEC X1, X0 MOVUPS 96(AX), X1 AESDEC X1, X0 MOVUPS 112(AX), X1 AESDEC X1, X0 MOVUPS 128(AX), X1 AESDEC X1, X0 MOVUPS 144(AX), X1 AESDECLAST X1,...
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Sep 25 19:53:19 UTC 2025 - 642.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/operand_test.go
{"$~(1<<63)", "$9223372036854775807"}, {"$~0x3F", "$-64"}, {"$~15", "$-16"}, {"(((8)&0xf)*4)(SP)", "32(SP)"}, {"(((8-14)&0xf)*4)(SP)", "40(SP)"}, {"(6+8)(AX)", "14(AX)"}, {"(8*4)(BP)", "32(BP)"}, {"(AX)", "(AX)"}, {"(AX)(CX*8)", "(AX)(CX*8)"}, {"(BP)(CX*4)", "(BP)(CX*4)"}, {"(BP)(DX*4)", "(BP)(DX*4)"}, {"(BP)(R8*4)", "(BP)(R8*4)"}, {"(BX)", "(BX)"}, {"(DI)", "(DI)"},Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Tue Aug 29 18:31:05 UTC 2023 - 23.9K bytes - Viewed (0) -
lib/fips140/v1.1.0-rc1.zip
JB Ldec128 MOVUPS (AX), X1 AESDEC X1, X0 MOVUPS 16(AX), X1 AESDEC X1, X0 ADDQ $0x20, AX Ldec192: MOVUPS (AX), X1 AESDEC X1, X0 MOVUPS 16(AX), X1 AESDEC X1, X0 ADDQ $0x20, AX Ldec128: MOVUPS (AX), X1 AESDEC X1, X0 MOVUPS 16(AX), X1 AESDEC X1, X0 MOVUPS 32(AX), X1 AESDEC X1, X0 MOVUPS 48(AX), X1 AESDEC X1, X0 MOVUPS 64(AX), X1 AESDEC X1, X0 MOVUPS 80(AX), X1 AESDEC X1, X0 MOVUPS 96(AX), X1 AESDEC X1, X0 MOVUPS 112(AX), X1 AESDEC X1, X0 MOVUPS 128(AX), X1 AESDEC X1, X0 MOVUPS 144(AX), X1 AESDECLAST X1,...
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Dec 11 16:27:41 UTC 2025 - 663K bytes - Viewed (0) -
src/cmd/asm/internal/lex/lex_test.go
}, { "LOAD macro", lines( "#define LOAD(off, reg) \\", "\tMOVBLZX (off*4)(R12), reg \\", "\tADDB reg, DX", "", "LOAD(8, AX)", ), "\n.\n.MOVBLZX.(.8.*.4.).(.R12.).,.AX.\n.ADDB.AX.,.DX.\n", }, { "nested multiline macro", lines( "#define KEYROUND(xmm, load, off, r1, r2, index) \\", "\tMOVBLZX (BP)(DX*4), R8 \\", "\tload((off+1), r2) \\",Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Tue Aug 29 07:48:38 UTC 2023 - 5.8K bytes - Viewed (0) -
doc/asm.html
For example, the sequence to load <code>g</code> and <code>m</code> using <code>CX</code> looks like this: </p> <pre> #include "go_tls.h" #include "go_asm.h" ... get_tls(CX) MOVL g(CX), AX // Move g into AX. MOVL g_m(AX), BX // Move g.m into BX. </pre> <p> The <code>get_tls</code> macro is also defined on <a href="#amd64">amd64</a>. </p> <p> Addressing modes: </p> <ul> <li>
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Fri Nov 14 19:09:46 UTC 2025 - 36.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/parse.go
if tok == scanner.EOF { p.errorf("unexpected EOF") return "", "", nil, false } // Split operands on comma. Also, the old syntax on x86 for a "register pair" // was AX:DX, for which the new syntax is DX, AX. Note the reordering. if tok == '\n' || tok == ';' || (nesting == 0 && (tok == ',' || tok == ':')) { if tok == ':' { // Remember this location so we can swap the operands below. if colon >= 0 {Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Wed Nov 12 03:59:40 UTC 2025 - 37.3K bytes - Viewed (0)