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Results 1 - 7 of 7 for 1x26x26x64xf32 (0.39 sec)
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tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_gpu_cc_70.mlir
padding = "VALID", strides = [1, 1, 1, 1] } : (tensor<4xi32>, tensor<1x28x28x64xf32>, tensor<1x28x28x64xf32>) -> tensor<1x28x28x64xf32> func.return %0 : tensor<1x28x28x64xf32> } // CHECK-LABEL: func @transposeConv2DBackpropInput_f16 func.func @transposeConv2DBackpropInput_f16( %input_size: tensor<4xi32>, %filter: tensor<1x64x28x28xf16>,
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 21 08:41:18 UTC 2022 - 8.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_gpu_cc_60.mlir
is_training = true } : (tensor<1x28x28x64xf32>, tensor<1x28x28x64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>) -> (tensor<1x28x28x64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>) func.return %x_backprop : tensor<1x28x28x64xf32> } // CHECK-LABEL: func @transposeFusedBatchNormGradV3_f16
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 21 08:41:18 UTC 2022 - 5.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_to_nchw.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 9K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/stablehlo/tests/optimize_layout.mlir
// CHECK: stablehlo.return %[[MAX]] : tensor<f32> // CHECK: }) : (tensor<1x114x114x64xf32>, tensor<f32>) -> tensor<1x56x56x64xf32> // CHECK: %[[TPOS:.*]] = stablehlo.transpose %[[REDUCE]], dims = [0, 3, 1, 2] // CHECK: : (tensor<1x56x56x64xf32>) -> tensor<1x64x56x56xf32> // CHECK: return %[[TPOS]] : tensor<1x64x56x56xf32> func.func @commute_transpose_reduce_window(
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 21:59:06 UTC 2024 - 2.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_move_transposes_end.mlir
%2 = "tf.MaxPool"(%1) { data_format = "NHWC", ksize = [1, 3, 3, 1], padding = "SAME", strides = [1, 2, 2, 1] } : (tensor<1x112x112x64xf32>) -> tensor<1x56x56x64xf32> func.return %2 : tensor<1x56x56x64xf32> } // CHECK-LABEL: func @fold_into_mean func.func @fold_into_mean(%arg0: tensor<1x64x112x112xf32>) -> tensor<1x64xf32> {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 9.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_to_nhwc.mlir
// CHECK: "tf.FusedBatchNormV3" // CHECK-SAME: (%[[ARG_TRANSPOSE]], %arg1, %arg1, %arg1, %arg1) // CHECK-SAME: data_format = "NHWC" // CHECK-SAME: (tensor<1x28x28x64xf32>, tensor<64xf32>, // CHECK-SAME: -> (tensor<1x28x28x64xf32>, tensor<64xf32>, // CHECK: %[[RES_PERM:.*]] = "tf.Const"() // CHECK-SAME: <{value = dense<[0, 3, 1, 2]> : tensor<4xi64>}>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 4.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/stablehlo/tests/composite-lowering.mlir
// CHECK-DAG: %[[VAL_3:.*]] = arith.constant dense<32> : tensor<2xi32> // CHECK-DAG: %[[VAL_4:.*]] = "tfl.resize_bilinear"(%[[VAL_2]], %[[VAL_3]]) <{align_corners = false, half_pixel_centers = true}> : (tensor<1x16x16x64xf32>, tensor<2xi32>) -> tensor<1x32x32x64xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Jun 06 18:45:51 UTC 2024 - 32.6K bytes - Viewed (0)