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Results 1 - 10 of 15 for 0xffffff (0.03 seconds)
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src/archive/tar/stat_unix.go
// Copied from golang.org/x/sys/unix/dev_darwin.go. major := uint32((dev >> 24) & 0xff) minor := uint32(dev & 0xffffff) h.Devmajor, h.Devminor = int64(major), int64(minor) case "dragonfly": // Copied from golang.org/x/sys/unix/dev_dragonfly.go. major := uint32((dev >> 8) & 0xff) minor := uint32(dev & 0xffff00ff) h.Devmajor, h.Devminor = int64(major), int64(minor) case "freebsd":
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Fri Mar 15 16:01:50 GMT 2024 - 3.2K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
AND $0xff00ff, R2 // AND $16711935, R2 // fb1f80d2fb1fa0f242001b8a AND $0xff00ffff, R1 // AND $4278255615, R1 // fbff9fd21be0bff221001b8a ANDS $0xffff, R2 // ANDS $65535, R2 // 423c40f2 AND $0x7fffffff, R3 // AND $2147483647, R3 // 63784092
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Mon Nov 10 17:34:13 GMT 2025 - 96.1K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/armerror.s
MOVW R1, R0<<0(F1) // ERROR "illegal base register" MOVB R2, R0<<0(F1) // ERROR "illegal base register" MOVF 0x00ffffff(F2), F1 // ERROR "illegal base register" MOVD 0x00ffffff(F2), F1 // ERROR "illegal base register" MOVF F2, 0x00ffffff(F2) // ERROR "illegal base register" MOVD F2, 0x00ffffff(F2) // ERROR "illegal base register" MULS.S R1, R2, R3, R4 // ERROR "invalid .S suffix"
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Wed Oct 23 15:18:14 GMT 2024 - 14.5K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/arm.s
MOVB.W 0x00ffffff(R2), R1 // MOVB.W 16777215(R2), R1 MOVB -0x00ffffff(R2), R1 // MOVB -16777215(R2), R1 MOVB.P -0x00ffffff(R2), R1 // MOVB.P -16777215(R2), R1 MOVB.W -0x00ffffff(R2), R1 // MOVB.W -16777215(R2), R1 MOVBS R1, 0x00ffffff(R2) // MOVBS R1, 16777215(R2) MOVBS.W R1, 0x00ffffff(R2) // MOVBS.W R1, 16777215(R2) MOVBS.P R1, 0x00ffffff(R2) // MOVBS.P R1, 16777215(R2)
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Fri Dec 15 20:51:01 GMT 2023 - 69K bytes - Click Count (0) -
src/archive/zip/zip_test.go
t.Fatal(err) } } } t.Run("uint32max-2_NoZip64", func(t *testing.T) { t.Parallel() if generatesZip64(t, gen(0xfffffffe)) { t.Error("unexpected zip64") } }) t.Run("uint32max-1_Zip64", func(t *testing.T) { t.Parallel() if !generatesZip64(t, gen(0xffffffff)) { t.Error("expected zip64") } }) } // At 16k records, we need to generate a zip64 file.
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu May 23 01:00:11 GMT 2024 - 19.6K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/armv6.s
MOVF.NE F3, -0x20(g) // MOVF.NE F3, -32(g) // 083a0a1d MOVD F3, -0x20(g) // MOVD F3, -32(g) // 083b0aed MOVF 0x00ffffff(R2), F1 // MOVF 16777215(R2), F1 MOVD 0x00ffffff(R2), F1 // MOVD 16777215(R2), F1 MOVF F2, 0x00ffffff(R2) // MOVF F2, 16777215(R2) MOVD F2, 0x00ffffff(R2) // MOVD F2, 16777215(R2) MOVF F0, math·Exp(SB) // MOVF F0, math.Exp(SB) MOVF math·Exp(SB), F0 // MOVF math.Exp(SB), F0
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Wed Oct 23 15:18:14 GMT 2024 - 4.7K bytes - Click Count (0) -
src/archive/zip/reader.go
return nil, 0, errors.New("zip: invalid comment length") } d.comment = string(b[:l]) // These values mean that the file can be a zip64 file if d.directoryRecords == 0xffff || d.directorySize == 0xffff || d.directoryOffset == 0xffffffff { p, err := findDirectory64End(r, directoryEndOffset) if err == nil && p >= 0 { directoryEndOffset = p err = readDirectory64End(r, p, d) } if err != nil {
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Tue Mar 11 22:19:38 GMT 2025 - 28.4K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/arm64error.s
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Tue Oct 14 19:00:00 GMT 2025 - 38.4K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
MOV $0x7ffff000, X5 // MOV $2147479552, X5 // b7f2ff7f MOV $-0x7ffff000, X5 // MOV $-2147479552, X5 // b7120080 MOV $0x7fffffff, X5 // MOV $2147483647, X5 // b70200809b82f2ff MOV $-0x7fffffff, X5 // MOV $-2147483647, X5 // b70200809b821200 // Converted to load and shift(s) MOV $0xffffffff, X5 // MOV $4294967295, X5 // 9302f0ff93d20202 MOV $0x100000000, X5 // MOV $4294967296, X5 // 9302100093920202
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu Nov 13 12:17:37 GMT 2025 - 73.7K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
TST $0xfffffff0, LR // TST $4294967280, R30 // df6f7cf2 TSTW R10@>21, R2 // 5f54ca6a TST R17<<11, R24 // 1f2f11ea ANDSW $0x80000007, R9, ZR // ANDSW $2147483655, R9, ZR // 3f0d0172 ANDS $0xfffffff0, LR, ZR // ANDS $4294967280, R30, ZR // df6f7cf2
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Mon Jul 24 01:11:41 GMT 2023 - 43.9K bytes - Click Count (0)