runs-on: ubuntu-latest
    permissions:
      issues: write
      pull-requests: write
    steps:
      - name: Awaiting response issues
        uses: actions/stale@5f858e3efba33a5ca4407a664cc011ad407f2008 # v10.1.0
        with:
          #Comma separated list of labels that can be assigned to issues to exclude them from being marked as stale
          exempt-issue-labels: 'override-stale'

	VMOVD	$0x8040201008040201, V20                              // VMOVD	$-9205322385119247871, V20
	VMOVQ	$0x7040201008040201, $0x8040201008040201, V10         // VMOVQ	$8088500183983456769, $-9205322385119247871, V10
	VMOVQ	$0x8040201008040202, $0x7040201008040201, V20         // VMOVQ	$-9205322385119247870, $8088500183983456769, V20

// mov(to/from sp)

	VST1.P	[V4.S4], 8(R1)                                   // ERROR "invalid post-increment offset"
	VLD1.P	32(R1), [V8.S4, V9.S4, V10.S4]                   // ERROR "invalid post-increment offset"
	VLD1.P	48(R1), [V7.S4, V8.S4, V9.S4, V10.S4]            // ERROR "invalid post-increment offset"
	VPMULL	V1.D1, V2.H4, V3.Q1                              // ERROR "invalid arrangement"

V6.B16 AESMC V6.B16, V6.B16 AESE V9.B16, V7.B16 AESMC V7.B16, V7.B16 Lenc192: VLD1.P 32(XK), [V10.B16, V11.B16] AESE V10.B16, V0.B16 AESMC V0.B16, V0.B16 AESE V10.B16, V1.B16 AESMC V1.B16, V1.B16 AESE V10.B16, V2.B16 AESMC V2.B16, V2.B16 AESE V10.B16, V3.B16 AESMC V3.B16, V3.B16 AESE V10.B16, V4.B16 AESMC V4.B16, V4.B16 AESE V10.B16, V5.B16 AESMC V5.B16, V5.B16 AESE V10.B16, V6.B16 AESMC V6.B16, V6.B16 AESE V10.B16, V7.B16 AESMC V7.B16, V7.B16 AESE V11.B16, V0.B16 AESMC V0.B16, V0.B16 AESE V11.B16, V1.B16...

	VCOMPRESSVM	X10, V2, V3			// ERROR "expected vector register in vs1 position"
	VMV1RV		X10, V1				// ERROR "expected vector register in vs2 position"
	VMV2RV		X10, V10			// ERROR "expected vector register in vs2 position"
	VMV4RV		X10, V4				// ERROR "expected vector register in vs2 position"
	VMV8RV		X10, V0				// ERROR "expected vector register in vs2 position"

	VMOVQ		V5.W[2], R7     // a7e8ef72
	VMOVQ		V6.V[1], R8     // c8f4ef72
	VMOVQ		V7.BU[0], R4    // e480f372
	VMOVQ		V7.BU[1], R4    // e484f372
	VMOVQ		V9.BU[3], R5    // 258df372
	VMOVQ		V10.HU[2], R6   // 46c9f372
	VMOVQ		V11.WU[2], R7   // 67e9f372
	VMOVQ		V31.VU[1], R8   // e8f7f372
	XVMOVQ		X1.W[2], R7     // 27c8ef76
	XVMOVQ		X6.V[2], R8     // c8e8ef76
	XVMOVQ		X8.WU[2], R7    // 07c9f376

	// 31.16.5: Vector Compress Instruction
	VCOMPRESSVM	V1, V2, V3			// d7a1205e

	// 31.16.6: Whole Vector Register Move
	VMV1RV		V2, V1				// d730209e
	VMV2RV		V12, V10			// 57b5c09e
	VMV4RV		V8, V4				// 57b2819e
	VMV8RV		V8, V0				// 57b0839e

	//
	// Privileged ISA
	//

	// 3.3.1: Environment Call and Breakpoint
	ECALL						// 73000000