p.errorf("register list: bad low register in `[%s`", loName)
		}
		return
	}
	if tok := p.next().ScanToken; tok != '-' {
		p.errorf("register list: expected '-' after `[%s`, found %s", loName, tok)
		return
	}
	hiName := p.next().String()
	hi, ok := p.arch.Register[hiName]
	if !ok {
		p.errorf("register list: bad high register in `[%s-%s`", loName, hiName)
		return
	}

	VADDVX		X10, V2, V1, V3			// ERROR "invalid vector mask register"
	VADDVI		$15, V4, V1, V2			// ERROR "invalid vector mask register"
	VSUBVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
	VSUBVX		X10, V2, V1, V3			// ERROR "invalid vector mask register"
	VRSUBVX		X10, V2, V1, V3			// ERROR "invalid vector mask register"
	VRSUBVI		$15, V4, V1, V2			// ERROR "invalid vector mask register"

	register["A0"] = riscv.REG_A0
	register["A1"] = riscv.REG_A1
	register["A2"] = riscv.REG_A2
	register["A3"] = riscv.REG_A3
	register["A4"] = riscv.REG_A4
	register["A5"] = riscv.REG_A5
	register["A6"] = riscv.REG_A6
	register["A7"] = riscv.REG_A7
	register["S2"] = riscv.REG_S2
	register["S3"] = riscv.REG_S3
	register["S4"] = riscv.REG_S4
	register["S5"] = riscv.REG_S5
	register["S6"] = riscv.REG_S6

	createCallback.Match(enableTransaction).Register("gorm:begin_transaction", BeginTransaction)
	createCallback.Register("gorm:before_create", BeforeCreate)
	createCallback.Register("gorm:save_before_associations", SaveBeforeAssociations(true))
	createCallback.Register("gorm:create", Create(config))
	createCallback.Register("gorm:save_after_associations", SaveAfterAssociations(true))
	createCallback.Register("gorm:after_create", AfterCreate)

        assertEquals("processed: template with params", result);
    }

    // Test register with null factory throws exception
    @Test
    public void test_register_nullFactory() {
        ComponentUtil.register(null, "scriptEngineFactory");

        try {
            testScriptEngine.register();
            fail("Should throw exception when factory is null");
        } catch (NullPointerException e) {

	CASPD	(R2, R3), (R2), (R9, R10)                        // ERROR "destination register pair must start from even register"
	CASPD	(R2, R4), (R2), (R8, R9)                         // ERROR "source register pair must be contiguous"
	CASPD	(R2, R3), (R2), (R8, R10)                        // ERROR "destination register pair must be contiguous"

        // Get the queryProcessor that was registered in parent class
        queryProcessor = ComponentUtil.getComponent("queryProcessor");

        // Register all query commands needed for testing
        new TermQueryCommand().register();
        new MatchAllQueryCommand().register();
        new PhraseQueryCommand().register();
        new BooleanQueryCommand().register();
        new PrefixQueryCommand().register();

                // Mock implementation
            }
        };

        // Register components
        ComponentUtil.register(searchEngineClient, "searchEngineClient");
        ComponentUtil.register(systemHelper, "systemHelper");
        ComponentUtil.setFessConfig(fessConfig);
        ComponentUtil.register(notificationHelper, "notificationHelper");

        // Execute

            };
            ComponentUtil.register(mockSystemHelper, "systemHelper");

            // Register mock FessConfig
            FessConfig mockConfig = new FessConfig.SimpleImpl() {
                @Override
                public Integer getThumbnailSystemMonitorIntervalAsInteger() {
                    return 60;
                }
            };
            ComponentUtil.register(mockConfig, "fessConfig");

				// both 1st operand and 3rd operand are (Rs, Rs+1) register pair.
				// And the register pair must be contiguous.
				if (a[0].Type != obj.TYPE_REGREG) || (a[2].Type != obj.TYPE_REGREG) {
					p.errorf("invalid addressing modes for 1st or 3rd operand to %s instruction, must be register pair", op)
					return
				}
				// For ARM64 CASP-like instructions, its 2nd destination operand is register pair(Rt, Rt+1) that can