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Results 1 - 6 of 6 for fh10 (0.05 sec)
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src/cmd/asm/internal/asm/testdata/riscv64.s
VFADDVV V1, V2, V3 // d7912002 VFADDVV V1, V2, V0, V3 // d7912000 VFADDVF F10, V2, V3 // d7512502 VFADDVF F10, V2, V0, V3 // d7512500 VFSUBVV V1, V2, V3 // d791200a VFSUBVV V1, V2, V0, V3 // d7912008 VFSUBVF F10, V2, V3 // d751250a VFSUBVF F10, V2, V0, V3 // d7512508 VFRSUBVF F10, V2, V3 // d751259e VFRSUBVF F10, V2, V0, V3 // d751259c
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 13 12:17:37 UTC 2025 - 73.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64validation.s
CLWSP 20(SP), F10 // ERROR "expected integer register in rd position" CLWSP 22(SP), X10 // ERROR "must be a multiple of 4" CLDSP 24(X5), X10 // ERROR "rs2 must be SP/X2" CLDSP 24(SP), X0 // ERROR "cannot use register X0" CLDSP 24(SP), F10 // ERROR "expected integer register in rd position" CLDSP 28(SP), X10 // ERROR "must be a multiple of 8" CFLDSP 32(X5), F10 // ERROR "rs2 must be SP/X2"
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 13 12:17:37 UTC 2025 - 42.1K bytes - Viewed (0) -
fess-crawler/src/main/resources/org/codelibs/fess/crawler/mime/tika-mimetypes.xml
<glob pattern="*.fhc"/> <glob pattern="*.fh4"/> <glob pattern="*.fh40"/> <glob pattern="*.fh5"/> <glob pattern="*.fh50"/> <glob pattern="*.fh7"/> <glob pattern="*.fh8"/> <glob pattern="*.fh9"/> <glob pattern="*.fh10"/> <glob pattern="*.fh11"/> <glob pattern="*.fh12"/> <glob pattern="*.ft7"/> <glob pattern="*.ft8"/> <glob pattern="*.ft9"/>
Registered: Sat Dec 20 11:21:39 UTC 2025 - Last Modified: Thu Oct 16 07:46:32 UTC 2025 - 320.2K bytes - Viewed (5) -
src/cmd/asm/internal/arch/arch.go
register["FS6"] = riscv.REG_FS6 register["FS7"] = riscv.REG_FS7 register["FS8"] = riscv.REG_FS8 register["FS9"] = riscv.REG_FS9 register["FS10"] = riscv.REG_FS10 register["FS11"] = riscv.REG_FS11 register["FT8"] = riscv.REG_FT8 register["FT9"] = riscv.REG_FT9 register["FT10"] = riscv.REG_FT10 register["FT11"] = riscv.REG_FT11 // Pseudo-registers. register["SB"] = RSB register["FP"] = RFP
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 13 12:17:37 UTC 2025 - 21.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
FMOVS F1, 1(R2) // 411000bc FMOVS F1, 4(R2) // 410400bd FMOVS F20, (R0) // 140000bd FMOVD F1, 1(R2) // 411000fc FMOVD F1, 8(R2) // 410400fd FMOVD F20, (R2) // 540000fd FMOVQ F0, 32(R5)// a008803d FMOVQ F10, 65520(R10) // 4afdbf3d FMOVQ F11, 64(RSP) // eb13803d FMOVQ F11, 8(R20) // 8b82803c FMOVQ F11, 4(R20) // 8b42803c MOVB 1(R1), R2 // 22048039 MOVH 1(R1), R2 // 22108078
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Mon Nov 10 17:34:13 UTC 2025 - 96.1K bytes - Viewed (0) -
lib/fips140/v1.1.0-rc1.zip
zi := *idx(z, i) z0 := zi & mask32 z1 := zi >> 32 c0 := carry & mask32 c1 := carry >> 32 w00 := x0*y0 + z0 + c0 l00 := w00 & mask32 h00 := w00 >> 32 w01 := x0*y1 + z1 + h00 l01 := w01 & mask32 h01 := w01 >> 32 w10 := x1*y0 + c1 + l01 h10 := w10 >> 32 carry = x1*y1 + h10 + h01 *idx(z, i) = w10<<32 + l00 } return carry } func addMulVVW1024(z, x *uint, y uint) (c uint) { return addMulVVWWasm(z, x, y, 1024/_W) } func addMulVVW1536(z, x *uint, y uint) (c uint) { return addMulVVWWasm(z, x, y, 1536/_W) }...
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Dec 11 16:27:41 UTC 2025 - 663K bytes - Viewed (0)