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Results 1 - 6 of 6 for d2 (0.01 seconds)

  1. src/cmd/asm/internal/asm/testdata/arm64error.s

    	VBIF	V0.D2, V1.D2, V2.D2                              // ERROR "invalid arrangement"
    	VUADDW	V9.B8, V12.H8, V14.B8                            // ERROR "invalid arrangement"
    	VUADDW2	V9.B8, V12.S4, V14.S4                            // ERROR "operand mismatch"
    	VUMAX	V1.D2, V2.D2, V3.D2                              // ERROR "invalid arrangement"
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Tue Feb 24 21:29:25 GMT 2026
    - 38.5K bytes
    - Click Count (0)
  2. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	FCVTZUD F25, R22                           // 3603799e
    	//TODO VFDIV V6.D2, V1.D2, V27.D2          // 3bfc666e
    	FDIVS F16, F10, F20                        // 5419301e
    	FDIVD F11, F25, F30                        // 3e1b6b1e
    	FMADDS F15, F2, F8, F1                     // 01090f1f
    	FMADDD F15, F21, F25, F9                   // 29574f1f
    	//TODO VFMAX V23.D2, V27.D2, V14.D2        // 6ef7774e
    	FMAXS F5, F28, F27                         // 9b4b251e
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Tue Feb 24 21:29:25 GMT 2026
    - 44K bytes
    - Click Count (0)
  3. src/cmd/asm/internal/asm/testdata/arm64.s

    	SHA512H	V2.D2, V1, V0                   // 208062ce
    	SHA512H2	V4.D2, V3, V2           // 628464ce
    	SHA512SU0	V9.D2, V8.D2            // 2881c0ce
    	SHA512SU1	V7.D2, V6.D2, V5.D2     // c58867ce
    	VRAX1	V26.D2, V29.D2, V30.D2          // be8f7ace
    	VXAR	$63, V27.D2, V21.D2, V26.D2     // bafe9bce
    	VPMULL	V2.D1, V1.D1, V3.Q1             // 23e0e20e
    	VPMULL2	V2.D2, V1.D2, V4.Q1             // 24e0e24e
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Fri Feb 27 20:41:17 GMT 2026
    - 96.2K bytes
    - Click Count (0)
  4. src/cmd/asm/internal/asm/testdata/arm64sveerror.s

    	ZFMAXNMP Z1.S, Z26.S, P14.M, Z7.D                 // ERROR "illegal combination from SVE"
    	ZFMAXNMQV Z1.S, P13.Z, V11.D2                     // ERROR "illegal combination from SVE"
    	ZFMAXP Z1.S, Z26.S, P14.M, Z7.D                   // ERROR "illegal combination from SVE"
    	ZFMAXQV Z1.S, P13.Z, V11.D2                       // ERROR "illegal combination from SVE"
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Fri Mar 20 17:02:17 GMT 2026
    - 50.6K bytes
    - Click Count (0)
  5. src/test/java/org/codelibs/fess/helper/CrawlingConfigHelperTest.java

                    list.add((DataConfig) crawlingConfigHelper.getCrawlingConfig("D2"));
                    list.add((DataConfig) crawlingConfigHelper.getCrawlingConfig("D3"));
                    return list;
                }
            }, DataConfigBhv.class.getCanonicalName());
            final List<DataConfig> configList = crawlingConfigHelper.getDataConfigListByIds(List.of("D1", "D2", "D3"));
            assertEquals(3, configList.size());
    Created: Tue Mar 31 13:07:34 GMT 2026
    - Last Modified: Fri Mar 13 23:01:26 GMT 2026
    - 35.3K bytes
    - Click Count (0)
  6. src/cmd/asm/internal/arch/arm64.go

    		curQ = 0
    	case "H8":
    		curSize = 1
    		curQ = 1
    	case "S2":
    		curSize = 2
    		curQ = 0
    	case "S4":
    		curSize = 2
    		curQ = 1
    	case "D1":
    		curSize = 3
    		curQ = 0
    	case "D2":
    		curSize = 3
    		curQ = 1
    	default:
    		return 0, errors.New("invalid arrangement in ARM64 register list")
    	}
    	return (int64(curQ) & 1 << 30) | (int64(curSize&3) << 10), nil
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Fri Mar 20 17:02:17 GMT 2026
    - 6K bytes
    - Click Count (0)
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