ADDS	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	ADDSW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	SUB	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	SUBW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"

	SWPLD	R5, (RSP), R7                        // e78365f8
	SWPLW	R5, (R6), R7                         // c78065b8
	SWPLW	R5, (RSP), R7                        // e78365b8
	SWPLH	R5, (R6), R7                         // c7806578
	SWPLH	R5, (RSP), R7                        // e7836578
	SWPLB	R5, (R6), R7                         // c7806538
	SWPLB	R5, (RSP), R7                        // e7836538

	CMNW $(2<<12), R5                          // CMNW $8192, R5                // bf084031
	CMN $(8<<12), R12                          // CMN $32768, R12               // 9f2140b1
	CMN R6->0, R3                              // 7f0086ab
	CMN R6, R3                                 // 7f0006ab
	CMNW R30, R5                               // bf001e2b
	CMNW $2, R5                                // bf080031

		a.Scale = int16(scale)
	}
}

// registerList parses an ARM or ARM64 register list expression, a list of
// registers in []. There may be comma-separated ranges or individual
// registers, as in [R1,R3-R5] or [V1.S4, V2.S4, V3.S4, V4.S4].
// For ARM, only R0 through R15 may appear.
// For ARM64, V0 through V31 with arrangement may appear.
//
// For 386/AMD64 register list specifies 4VNNIW-style multi-source operand.