MOVDBR (R3)(R0), R5             // 7ca01c28
	MOVDBR (R3), R5                 // 7ca01c28
	MOVWBR (R3)(R4), R5             // 7ca41c2c
	MOVWBR (R3)(R0), R5             // 7ca01c2c
	MOVWBR (R3), R5                 // 7ca01c2c
	MOVHBR (R3)(R4), R5             // 7ca41e2c
	MOVHBR (R3)(R0), R5             // 7ca01e2c
	MOVHBR (R3), R5                 // 7ca01e2c
	OR $0, R0, R0

	SLL	R4, R5			// a5101700
	SLL	R4, R5, R6		// a6101700
	SRL	R4, R5			// a5901700
	SRL	R4, R5, R6	 	// a6901700
	SRA	R4, R5			// a5101800
	SRA	R4, R5, R6	 	// a6101800
	ROTR	R4, R5			// a5101b00
	ROTR	R4, R5, R6		// a6101b00
	SLLV	R4, R5			// a5901800
	SLLV	R4, R5, R6		// a6901800
	ROTRV	R4, R5			// a5901b00
	ROTRV	R4, R5, R6		// a6901b00
	CLOW	R4, R5			// 85100000
	CLZW	R4, R5			// 85140000
	CTOW	R4, R5			// 85180000

	SLW	R2, R3, R6              // eb63200000df
	SLD	$4, R3, R6              // eb630004000d
	SLD	R2, R3, R6              // eb632000000d
	SRAD	$4, R5, R8              // eb850004000a
	SRAD	R3, R5, R8              // eb853000000a
	SRAW	$4, R5, R8              // eb85000400dc
	SRAW	R3, R5, R8              // eb85300000dc
	RLL	R1, R2, R3              // eb321000001d
	RLL	$4, R2, R3              // eb320004001d

	XTABU	R0->24, R2         // ERROR "illegal shift"
	XTAHU	R0@>1, R2          // ERROR "illegal shift"
	XTAB	R0>>8, R5, R2      // ERROR "illegal shift"
	XTAH	R0<<16, R5, R2     // ERROR "illegal shift"
	XTABU	R0->24, R5, R2     // ERROR "illegal shift"
	XTAHU	R0@>1, R5, R2      // ERROR "illegal shift"
	AND.W	R0, R1             // ERROR "invalid .W suffix"
	ORR.P	R2, R3, R4         // ERROR "invalid .P suffix"

	MOVFD	F0, F1        // c01ab7ee
	MOVDF	F4, F5        // c45bb7ee

	LDREX	(R8), R9      // 9f9f98e1
	LDREXB	(R11), R12    // 9fcfdbe1
	LDREXD	(R11), R12    // 9fcfbbe1
	STREX	R3, (R4), R5  // STREX  (R4), R3, R5 // 935f84e1
	STREXB	R8, (R9), g   // STREXB (R9), R8, g  // 98afc9e1
	STREXD	R8, (R9), g   // STREXD (R9), R8, g  // 98afa9e1

	CMPF    F8, F9        // c89ab4ee10faf1ee
	CMPD.CS F4, F5        // c45bb42e10faf12e

		a.Scale = int16(scale)
	}
}

// registerList parses an ARM or ARM64 register list expression, a list of
// registers in []. There may be comma-separated ranges or individual
// registers, as in [R1,R3-R5] or [V1.S4, V2.S4, V3.S4, V4.S4].
// For ARM, only R0 through R15 may appear.
// For ARM64, V0 through V31 with arrangement may appear.
//
// For 386/AMD64 register list specifies 4VNNIW-style multi-source operand.