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Results 1 - 7 of 7 for LXVD2X (0.11 sec)
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src/crypto/subtle/xor_ppc64x.s
// Load 4 vectors of a and b // XOR the corresponding vectors // from a and b and store the result loop64: LXVD2X (R4)(R8), VS32 LXVD2X (R4)(R10), VS34 LXVD2X (R4)(R14), VS36 LXVD2X (R4)(R15), VS38 LXVD2X (R5)(R8), VS33 LXVD2X (R5)(R10), VS35 LXVD2X (R5)(R14), VS37 LXVD2X (R5)(R15), VS39 XXLXOR VS32, VS33, VS32 XXLXOR VS34, VS35, VS34 XXLXOR VS36, VS37, VS36 XXLXOR VS38, VS39, VS38
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 2.9K bytes - Viewed (0) -
src/crypto/aes/asm_ppc64x.s
MOVD $128, R20 \ MOVD $144, R21 \ LXVD2X (R0+Rkeyp), V6 \ ADD $16, Rkeyp \ BEQ CR1, L_start10 \ BEQ CR2, L_start12 \ LXVD2X (R0+Rkeyp), V7 \ LXVD2X (R12+Rkeyp), V8 \ ADD $32, Rkeyp \ L_start12: \ LXVD2X (R0+Rkeyp), V9 \ LXVD2X (R12+Rkeyp), V10 \ ADD $32, Rkeyp \ L_start10: \ LXVD2X (R0+Rkeyp), V11 \ LXVD2X (R12+Rkeyp), V12 \ LXVD2X (R14+Rkeyp), V13 \ LXVD2X (R15+Rkeyp), V14 \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 20 18:05:32 UTC 2024 - 18.6K bytes - Viewed (0) -
src/math/big/arith_ppc64x.s
VSPLTB $7, V6, V4 MTVSRD R5, VS39 // ŝ VSPLTB $7, V7, V2 ADD $-2, R4, R16 PCALIGN $16 loopback: ADD $-1, R8, R10 SLD $3, R10 LXVD2X (R6)(R10), VS32 // load x[i-1], x[i] SLD $3, R8, R12 LXVD2X (R6)(R12), VS33 // load x[i], x[i+1] VSRD V0, V4, V3 // x[i-1]>>s, x[i]>>s VSLD V1, V2, V5 // x[i]<<ŝ, x[i+1]<<ŝ
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 16.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
VSHASIGMAW $1, $15, V1, V2 // 10418e82 VSHASIGMAD $2, V1, $15, V2 // 104196c2 VSHASIGMAD $2, $15, V1, V2 // 104196c2 LXVD2X (R3)(R4), VS1 // 7c241e98 LXVD2X (R3)(R0), VS1 // 7c201e98 LXVD2X (R3), VS1 // 7c201e98 LXVDSX (R3)(R4), VS1 // 7c241a98 LXVDSX (R3)(R0), VS1 // 7c201a98 LXVDSX (R3), VS1 // 7c201a98
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
unsafePoint: true, }, // R31 is temp register // Loop code: // MOVD len/32,R31 set up loop ctr // MOVD R31,CTR // MOVD $16,R31 index register // loop: // LXVD2X (R0)(R4),VS32 // LXVD2X (R31)(R4),VS33 // ADD R4,$32 increment src // STXVD2X VS32,(R0)(R3) // STXVD2X VS33,(R31)(R3) // ADD R3,$32 increment dst // BC 16,0,loop branch ctr
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/compile/internal/ppc64/ssa.go
// number of moves are generated based on the // size. // When moving >= 64 bytes a loop is used // MOVD len/32,REG_TMP // MOVD REG_TMP,CTR // MOVD $16,REG_TMP // top: // LXVD2X (R0)(R21),VS32 // LXVD2X (R31)(R21),VS33 // ADD $32,R21 // STXVD2X VS32,(R0)(R20) // STXVD2X VS33,(R31)(R20) // ADD $32,R20 // BC 16,0,top // Bytes not moved by this loop are moved
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 55.4K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm9.go
case AVSBOX: /* vsbox */ opset(AVSBOX, r0) case AVSHASIGMA: /* vshasigmaw, vshasigmad */ opset(AVSHASIGMAW, r0) opset(AVSHASIGMAD, r0) case ALXVD2X: /* lxvd2x, lxvdsx, lxvw4x, lxvh8x, lxvb16x */ opset(ALXVDSX, r0) opset(ALXVW4X, r0) opset(ALXVH8X, r0) opset(ALXVB16X, r0) case ALXV: /* lxv */ opset(ALXV, r0)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 13:55:28 UTC 2024 - 156.1K bytes - Viewed (0)