MOVW	y+65540(FP), R4			// 1e020014de8f1000c4338028
	MOVWU	y+65540(FP), R4			// 1e020014de8f1000c433802a
	MOVV	y+65540(FP), R4			// 1e020014de8f1000c433c028
	MOVB	y+65540(FP), R4			// 1e020014de8f1000c4330028
	MOVBU	y+65540(FP), R4			// 1e020014de8f1000c433002a
	MOVW	y+4097(FP), R4			// 3e000014de8f1000c4278028
	MOVWU	y+4097(FP), R4			// 3e000014de8f1000c427802a
	MOVV	y+4097(FP), R4			// 3e000014de8f1000c427c028

	ABSF	F4, F5			// 85041401
	MOVVF	F4, F5			// 85181d01
	MOVF	F4, F5			// 85941401
	MOVD	F4, F5			// 85981401
	MOVW	R4, result+16(FP)	// 64608029
	MOVWU	R4, result+16(FP)	// 64608029
	MOVV	R4, result+16(FP)	// 6460c029
	MOVB	R4, result+16(FP)	// 64600029
	MOVBU	R4, result+16(FP)	// 64600029
	MOVW	R4, 1(R5)		// a4048029
	MOVWU	R4, 1(R5)		// a4048029
	MOVV	R4, 1(R5)		// a404c029
	MOVB	R4, 1(R5)		// a4040029

	// Create maps for easy lookup of instruction names etc.
	for i, s := range x86.Register {
		register[s] = int16(i + x86.REG_AL)
	}
	// Pseudo-registers.
	register["SB"] = RSB
	register["FP"] = RFP
	register["PC"] = RPC
	if linkArch == &x86.Linkamd64 {
		// Alias g to R14
		register["g"] = x86.REGG
	}
	// Register prefix not used on this architecture.

	instructions := make(map[string]obj.As)

at the beginning, as in <code>first_arg+0(FP)</code> and <code>second_arg+8(FP)</code>.
(The meaning of the offset—offset from the frame pointer—distinct
from its use with <code>SB</code>, where it is an offset from the symbol.)
The assembler enforces this convention, rejecting plain <code>0(FP)</code> and <code>8(FP)</code>.
The actual name is semantically irrelevant but should be used to document

*[256]byte, dst []byte, src []byte, ctr *[16]byte, T *[16]byte, ks []uint32) // Requires: AES, PCLMULQDQ, SSE2, SSE4.1, SSSE3 TEXT ·gcmAesEnc(SB), $256-96 MOVQ productTable+0(FP), DI MOVQ dst_base+8(FP), DX MOVQ src_base+32(FP), SI MOVQ src_len+40(FP), R9 MOVQ ctr+56(FP), CX MOVQ T+64(FP), R8 MOVQ ks_base+72(FP), AX MOVQ ks_len+80(FP), R13 SHRQ $0x02, R13 DECQ R13 MOVOU bswapMask<>+0(SB), X15 MOVOU gcmPoly<>+0(SB), X14 MOVOU (R8), X8 PXOR X9, X9 PXOR X10, X10 MOVOU (CX), X0 MOVL 12(CX), R10 MOVOU (AX),...

	}
	p.get(')')
	a.Type = obj.TYPE_MEM
	if r1 < 0 {
		// Pseudo-register reference.
		if r2 != 0 {
			p.errorf("cannot use pseudo-register in pair")
			return
		}
		// For SB, SP, and FP, there must be a name here. 0(FP) is not legal.
		if name != "PC" && a.Name == obj.NAME_NONE {
			p.errorf("cannot reference %s without a symbol", name)
		}
		p.setPseudoRegister(a, name, false, prefix)
		return
	}
	a.Reg = r1

	ADC	$0, R1                           // 21001f9a
	ADCW	$0, R1                           // 21001f1a
	ADCS	$0, R1                           // 21001fba
	ADCSW	$0, R1                           // 21001f3a

// fp/simd instructions.
	VADDP	V1.B16, V2.B16, V3.B16          // 43bc214e
	VADDP	V1.S4, V2.S4, V3.S4             // 43bca14e
	VADDP	V1.D2, V2.D2, V3.D2             // 43bce14e
	VAND	V21.B8, V12.B8, V3.B8           // 831d350e

0.
72.40
072.40       // == 72.40
2.71828
1.e+0
6.67428e-11
1E6
.25
.12345E+5
1_5.         // == 15.0
0.15e+0_2    // == 15.0

0x1p-2       // == 0.25
0x2.p10      // == 2048.0
0x1.Fp+0     // == 1.9375
0X.8p-0      // == 0.5
0X_1FFFP-16  // == 0.1249847412109375
0x15e-2      // == 0x15e - 2 (integer subtraction)

0x.p1        // invalid: mantissa has no digits