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Results 1 - 4 of 4 for FLessEqual (0.34 sec)
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src/cmd/compile/internal/ssa/_gen/PPC64.rules
(Less(32|64)U x y) => (LessThan ((CMPWU|CMPU) x y)) (Leq(8|16) x y) => (LessEqual (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y))) (Leq(32|64) x y) => (LessEqual ((CMPW|CMP) x y)) (Leq(32|64)F x y) => (FLessEqual (FCMPU x y)) (Leq(8|16)U x y) => (LessEqual (CMPWU (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y))) (Leq(32|64)U x y) => (LessEqual (CMP(WU|U) x y)) // Absorb pseudo-ops into blocks.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
{name: "FLessThan", argLength: 1, reg: crgp}, // bool, true flags encode x<y false otherwise. {name: "LessEqual", argLength: 1, reg: crgp}, // bool, true flags encode x<=y false otherwise. {name: "FLessEqual", argLength: 1, reg: crgp}, // bool, true flags encode x<=y false otherwise; PPC <= === !> which is wrong for NaN {name: "GreaterThan", argLength: 1, reg: crgp}, // bool, true flags encode x>y false otherwise.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64.go
v.AddArg(v0) return true } } func rewriteValuePPC64_OpLeq32F(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block // match: (Leq32F x y) // result: (FLessEqual (FCMPU x y)) for { x := v_0 y := v_1 v.reset(OpPPC64FLessEqual) v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags) v0.AddArg2(x, y) v.AddArg(v0) return true } }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 360.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FLessEqual", argLen: 1, reg: regInfo{ outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, },
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)