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Results 1 - 4 of 4 for FLessThan (0.19 sec)

  1. src/cmd/compile/internal/ssa/_gen/PPC64.rules

    (Neq(32|64)F x y) => (NotEqual (FCMPU x y))
    
    (Less(8|16) x y)  => (LessThan (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
    (Less(32|64) x y) => (LessThan ((CMPW|CMP) x y))
    (Less(32|64)F x y) => (FLessThan (FCMPU x y))
    
    (Less(8|16)U x y)  => (LessThan (CMPWU (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y)))
    (Less(32|64)U x y) => (LessThan ((CMPWU|CMPU) x y))
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 53.2K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/PPC64Ops.go

    		{name: "NotEqual", argLength: 1, reg: crgp},      // bool, true flags encode x!=y false otherwise.
    		{name: "LessThan", argLength: 1, reg: crgp},      // bool, true flags encode  x<y false otherwise.
    		{name: "FLessThan", argLength: 1, reg: crgp},     // bool, true flags encode  x<y false otherwise.
    		{name: "LessEqual", argLength: 1, reg: crgp},     // bool, true flags encode  x<=y false otherwise.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 43.8K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/rewritePPC64.go

    		v.AddArg(v0)
    		return true
    	}
    }
    func rewriteValuePPC64_OpLess32F(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	b := v.Block
    	// match: (Less32F x y)
    	// result: (FLessThan (FCMPU x y))
    	for {
    		x := v_0
    		y := v_1
    		v.reset(OpPPC64FLessThan)
    		v0 := b.NewValue0(v.Pos, OpPPC64FCMPU, types.TypeFlags)
    		v0.AddArg2(x, y)
    		v.AddArg(v0)
    		return true
    	}
    }
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 360.2K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/opGen.go

    		reg: regInfo{
    			outputs: []outputInfo{
    				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
    			},
    		},
    	},
    	{
    		name:   "FLessThan",
    		argLen: 1,
    		reg: regInfo{
    			outputs: []outputInfo{
    				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
    			},
    		},
    	},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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