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Results 1 - 10 of 12 for FABS (0.06 sec)
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tensorflow/cc/framework/gradient_checker.cc
namespace tensorflow { namespace { // TODO(andydavis) Support returning relative error (as opposed to max error) // between theoretical and numerical jacobians: // fabs(jac_t - jac_n) / max(fabs(jac_t), fabs(jac_n)) // TODO(andydavis) Vectorize and/or multi-thread Jacobian computations if // performance becomes an issue. // BaseUnitsForType provides a list of typed unit values for each basis in the
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Sat Apr 13 05:57:22 UTC 2024 - 18.2K bytes - Viewed (0) -
test/codegen/math.go
} // Check that it's using integer registers func abs(x, y float64) { // amd64:"BTRQ\t[$]63" // arm64:"FABSD\t" // s390x:"LPDFR\t",-"MOVD\t" (no integer load/store) // ppc64x:"FABS\t" // riscv64:"FABSD\t" // wasm:"F64Abs" // arm/6:"ABSD\t" // mips64/hardfloat:"ABSD\t" // mips/hardfloat:"ABSD\t" sink64[0] = math.Abs(x) // amd64:"BTRQ\t[$]63","PXOR" (TODO: this should be BTSQ)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Apr 04 15:24:29 UTC 2024 - 6.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(Sqrt ...) => (FSQRT ...) (Sqrt32 ...) => (FSQRTS ...) (Floor ...) => (FFLOOR ...) (Ceil ...) => (FCEIL ...) (Trunc ...) => (FTRUNC ...) (Round ...) => (FROUND ...) (Copysign x y) => (FCPSGN y x) (Abs ...) => (FABS ...) (FMA ...) => (FMADD ...) // Lowering extension // Note: we always extend to 64 bits even though some ops don't need that many result bits. (SignExt8to(16|32|64) ...) => (MOVBreg ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/common/quantization_lib/quantization_utils.cc
new_scales.reserve(scales.size()); auto scales_iter = scales.begin(); for (const auto& f : factor_values) { new_scales.push_back(*scales_iter * std::fabs(FloatAttr::getValueAsDouble(f))); ++scales_iter; } // We are assuming symmetric quantization. auto new_ele_type = quant::UniformQuantizedPerAxisType::get(
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed May 08 02:10:16 UTC 2024 - 43.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/common/quantization_lib/quantization_utils.h
// the storage type is less than or equal to 8 bits. void TensorRangeSanityCheck(quantfork::StatisticsOp op, double& min, double& max) const { double range = std::fabs(max - min); if (num_bits <= 8 && range >= 10.0) { op.emitWarning() << "Tensor range is too wide to be quantized. Use tf.clip_by_value " "or tf.relu6 to narrow the tensor range. Range: "
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Apr 24 20:30:06 UTC 2024 - 41.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
FNMSUBS F1, F2, F3, F4 // ec8110fc FNMSUBSCC F1, F2, F3, F4 // ec8110fd FSEL F1, F2, F3, F4 // fc8110ee FSELCC F1, F2, F3, F4 // fc8110ef FABS F1, F2 // fc400a10 FNABS F1, F2 // fc400910 FABSCC F1, F2 // fc400a11 FNABSCC F1, F2 // fc400911 FNEG F1, F2 // fc400850
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/cmd/internal/obj/mips/asm0.go
case 32: /* fadd fr1,[fr2],fr3 */ r := p.Reg if r == obj.REG_NONE { r = p.To.Reg } o1 = OP_FRRR(c.oprrr(p.As), p.From.Reg, r, p.To.Reg) case 33: /* fabs fr1, fr3 */ o1 = OP_FRRR(c.oprrr(p.As), obj.REG_NONE, p.From.Reg, p.To.Reg) case 34: /* mov $con,fr ==> or/add $i,t; mov t,fr */ a := AADDU if o.a1 == C_ANDCON { a = AOR }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 17:46:09 UTC 2024 - 53.6K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/asm.go
case 32: // fadd fr1,[fr2],fr3 r := int(p.Reg) if r == 0 { r = int(p.To.Reg) } o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg)) case 33: // fabs fr1, fr3 o1 = OP_RRR(c.oprrr(p.As), uint32(0), uint32(p.From.Reg), uint32(p.To.Reg)) case 34: // mov $con,fr v := c.regoff(&p.From) a := AADDU if o.from1 == C_ANDCON { a = AOR }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 61.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64.go
} func rewriteValuePPC64_OpPPC64FNEG(v *Value) bool { v_0 := v.Args[0] // match: (FNEG (FABS x)) // result: (FNABS x) for { if v_0.Op != OpPPC64FABS { break } x := v_0.Args[0] v.reset(OpPPC64FNABS) v.AddArg(x) return true } // match: (FNEG (FNABS x)) // result: (FABS x) for { if v_0.Op != OpPPC64FNABS { break } x := v_0.Args[0]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 360.2K bytes - Viewed (0)