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Results 1 - 3 of 3 for F10 (0.01 sec)
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src/cmd/asm/internal/asm/testdata/riscv64.s
VFADDVV V1, V2, V3 // d7912002 VFADDVV V1, V2, V0, V3 // d7912000 VFADDVF F10, V2, V3 // d7512502 VFADDVF F10, V2, V0, V3 // d7512500 VFSUBVV V1, V2, V3 // d791200a VFSUBVV V1, V2, V0, V3 // d7912008 VFSUBVF F10, V2, V3 // d751250a VFSUBVF F10, V2, V0, V3 // d7512508 VFRSUBVF F10, V2, V3 // d751259e VFRSUBVF F10, V2, V0, V3 // d751259c
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 13 12:17:37 UTC 2025 - 73.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64validation.s
CLWSP 20(SP), F10 // ERROR "expected integer register in rd position" CLWSP 22(SP), X10 // ERROR "must be a multiple of 4" CLDSP 24(X5), X10 // ERROR "rs2 must be SP/X2" CLDSP 24(SP), X0 // ERROR "cannot use register X0" CLDSP 24(SP), F10 // ERROR "expected integer register in rd position" CLDSP 28(SP), X10 // ERROR "must be a multiple of 8" CFLDSP 32(X5), F10 // ERROR "rs2 must be SP/X2"
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 13 12:17:37 UTC 2025 - 42.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
FMOVS F1, 1(R2) // 411000bc FMOVS F1, 4(R2) // 410400bd FMOVS F20, (R0) // 140000bd FMOVD F1, 1(R2) // 411000fc FMOVD F1, 8(R2) // 410400fd FMOVD F20, (R2) // 540000fd FMOVQ F0, 32(R5)// a008803d FMOVQ F10, 65520(R10) // 4afdbf3d FMOVQ F11, 64(RSP) // eb13803d FMOVQ F11, 8(R20) // 8b82803c FMOVQ F11, 4(R20) // 8b42803c MOVB 1(R1), R2 // 22048039 MOVH 1(R1), R2 // 22108078
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Mon Nov 10 17:34:13 UTC 2025 - 96.1K bytes - Viewed (0)