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Results 1 - 10 of 13 for ADDV (0.05 sec)

  1. src/runtime/memmove_loong64.s

    words:
    	// do 8 bytes at a time if there is room
    	ADDV	$-7, R9, R6 // R6 is end pointer-7
    
    	PCALIGN	$16
    	SGTU	R6, R4, R8
    	BEQ	R8, out
    	MOVV	(R5), R7
    	ADDV	$8, R5
    	MOVV	R7, (R4)
    	ADDV	$8, R4
    	JMP	-6(PC)
    
    out:
    	BEQ	R4, R9, done
    	MOVB	(R5), R7
    	ADDV	$1, R5
    	MOVB	R7, (R4)
    	ADDV	$1, R4
    	JMP	-5(PC)
    done:
    	RET
    
    backward:
    	ADDV	R6, R5 // from-end pointer
    	ADDV	R4, R6, R9 // to-end pointer
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon May 13 15:04:25 UTC 2024
    - 1.8K bytes
    - Viewed (0)
  2. src/internal/bytealg/indexbyte_loong64.s

    TEXT ·IndexByte<ABIInternal>(SB),NOSPLIT,$0-40
    	// R4 = b_base
    	// R5 = b_len
    	// R6 = b_cap (unused)
    	// R7 = byte to find
    	AND	$0xff, R7
    	MOVV	R4, R6		// store base for later
    	ADDV	R4, R5		// end
    	ADDV	$-1, R4
    
    	PCALIGN	$16
    loop:
    	ADDV	$1, R4
    	BEQ	R4, R5, notfound
    	MOVBU	(R4), R8
    	BNE	R7, R8, loop
    
    	SUBV	R6, R4		// remove base
    	RET
    
    notfound:
    	MOVV	$-1, R4
    	RET
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon May 13 15:04:25 UTC 2024
    - 905 bytes
    - Viewed (0)
  3. src/runtime/memclr_loong64.s

    TEXT runtime·memclrNoHeapPointers<ABIInternal>(SB),NOSPLIT,$0-16
    	ADDV	R4, R5, R6
    
    	// if less than 8 bytes, do one byte at a time
    	SGTU	$8, R5, R8
    	BNE	R8, out
    
    	// do one byte at a time until 8-aligned
    	AND	$7, R4, R8
    	BEQ	R8, words
    	MOVB	R0, (R4)
    	ADDV	$1, R4
    	JMP	-4(PC)
    
    words:
    	// do 8 bytes at a time if there is room
    	ADDV	$-7, R6, R5
    
    	PCALIGN	$16
    	SGTU	R5, R4, R8
    	BEQ	R8, out
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon May 13 15:04:25 UTC 2024
    - 766 bytes
    - Viewed (0)
  4. src/reflect/asm_loong64.s

    	MOVV	32(R3), REGCTXT // restore REGCTXT
    
    	MOVV	REGCTXT, 8(R3)
    	MOVV	$argframe+0(FP), R20
    	MOVV	R20, 16(R3)
    	MOVV	R0, LOCAL_RETVALID(R3)
    	ADDV	$LOCAL_RETVALID, R3, R20
    	MOVV	R20, 24(R3)
    	ADDV	$LOCAL_REGARGS, R3, R20
    	MOVV	R20, 32(R3)
    	JAL	·callReflect(SB)
    	ADDV	$LOCAL_REGARGS, R3, R25	//unspillArgs using R25
    	JAL	runtime·unspillArgs(SB)
    	RET
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon May 13 15:04:25 UTC 2024
    - 2.7K bytes
    - Viewed (0)
  5. src/internal/bytealg/equal_loong64.s

    #define	REGCTXT	R29
    
    // memequal(a, b unsafe.Pointer, size uintptr) bool
    TEXT runtime·memequal<ABIInternal>(SB),NOSPLIT|NOFRAME,$0-25
    	BEQ	R4, R5, eq
    	ADDV	R4, R6, R7
    	PCALIGN	$16
    loop:
    	BNE	R4, R7, test
    	MOVV	$1, R4
    	RET
    test:
    	MOVBU	(R4), R9
    	ADDV	$1, R4
    	MOVBU	(R5), R10
    	ADDV	$1, R5
    	BEQ	R9, R10, loop
    
    	MOVB    R0, R4
    	RET
    eq:
    	MOVV	$1, R4
    	RET
    
    // memequal_varlen(a, b unsafe.Pointer) bool
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon May 13 15:04:25 UTC 2024
    - 875 bytes
    - Viewed (0)
  6. src/internal/bytealg/compare_loong64.s

    	BNE	R0, R15, byte_loop
    
    	PCALIGN	$16
    chunk16_loop:
    	BEQ	R0, R14, byte_loop
    	MOVV	(R4), R8
    	MOVV	(R6), R9
    	BNE	R8, R9, byte_loop
    	MOVV	8(R4), R16
    	MOVV	8(R6), R17
    	ADDV	$16, R4
    	ADDV	$16, R6
    	SUBVU	$1, R14
    	BEQ	R16, R17, chunk16_loop
    	SUBV	$8, R4
    	SUBV	$8, R6
    
    byte_loop:
    	BEQ	R4, R12, samebytes
    	MOVBU	(R4), R8
    	ADDVU	$1, R4
    	MOVBU	(R6), R9
    	ADDVU	$1, R6
    	BEQ	R8, R9, byte_loop
    
    byte_cmp:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon May 13 15:04:25 UTC 2024
    - 1.7K bytes
    - Viewed (0)
  7. src/cmd/internal/obj/loong64/asm_test.go

    	fmt.Fprintln(buf, "BNE R5, label23")
    
    	for i := 0; i <= genSize1; i++ {
    		fmt.Fprintln(buf, "ADDV $0, R0, R0")
    	}
    
    	fmt.Fprintln(buf, "label18:")
    	for i := 0; i <= (genSize2 - genSize1); i++ {
    		fmt.Fprintln(buf, "ADDV $0, R0, R0")
    	}
    
    	fmt.Fprintln(buf, "label23:")
    	fmt.Fprintln(buf, "ADDV $0, R0, R0")
    	fmt.Fprintln(buf, "RET")
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 15 17:39:37 UTC 2024
    - 2.2K bytes
    - Viewed (0)
  8. test/codegen/mathbits.go

    	// amd64:"NEGL","ADCQ","SBBQ","NEGQ"
    	// loong64: "ADDV", "SGTU"
    	// ppc64x: "ADDC", "ADDE", "ADDZE"
    	// s390x:"ADDE","ADDC\t[$]-1,"
    	// mips64:"ADDV","SGTU"
    	// riscv64: "ADD","SLTU"
    	return bits.Add(x, 7, ci)
    }
    
    func AddZ(x, y uint) (r, co uint) {
    	// arm64:"ADDS","ADC",-"ADCS",-"ADD\t",-"CMP"
    	// amd64:"ADDQ","SBBQ","NEGQ",-"NEGL",-"ADCQ"
    	// loong64: "ADDV", "SGTU"
    	// ppc64x: "ADDC", -"ADDE", "ADDZE"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 18:51:17 UTC 2024
    - 19.6K bytes
    - Viewed (0)
  9. src/runtime/asm_loong64.s

    	NO_LOCAL_POINTERS;			\
    	/* copy arguments to stack */		\
    	MOVV	arg+16(FP), R4;			\
    	MOVWU	argsize+24(FP), R5;			\
    	MOVV	R3, R12;				\
    	ADDV	$8, R12;			\
    	ADDV	R12, R5;				\
    	BEQ	R12, R5, 6(PC);				\
    	MOVBU	(R4), R6;			\
    	ADDV	$1, R4;			\
    	MOVBU	R6, (R12);			\
    	ADDV	$1, R12;			\
    	JMP	-5(PC);				\
    	/* set up argument registers */		\
    	MOVV	regArgs+40(FP), R25;		\
    	JAL	·unspillArgs(SB);		\
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon May 13 15:04:25 UTC 2024
    - 26.5K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	MOVV	R4, R5			// 85001500
    	MOVBU	R4, R5			// 85fc4303
    	SUB	R4, R5, R6		// a6101100
    	SUBV	R4, R5, R6		// a6901100
    	ADD	R4, R5, R6		// a6101000
    	ADDV	R4, R5, R6		// a6901000
    	AND	R4, R5, R6		// a6901400
    	SUB	R4, R5			// a5101100
    	SUBV	R4, R5			// a5901100
    	ADD	R4, R5			// a5101000
    	ADDV	R4, R5			// a5901000
    	AND	R4, R5			// a5901400
    	NEGW	R4, R5			// 05101100
    	NEGV	R4, R5			// 05901100
    	SLL	R4, R5			// a5101700
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 8.2K bytes
    - Viewed (0)
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