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Results 1 - 2 of 2 for A6 (0.03 sec)

  1. src/cmd/asm/internal/asm/testdata/amd64dynlinkerror.s

    	XORL R15, R15
    	RET
    TEXT ·a4(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    	XORQ R15, R15
    	RET
    TEXT ·a5(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    	XORL R15, R15
    	RET
    TEXT ·a6(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    	POPQ R15
    	PUSHQ R15
    	RET
    TEXT ·a7(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Thu Nov 20 19:05:03 UTC 2025
    - 4.9K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/arch/arch.go

    	register["A0"] = riscv.REG_A0
    	register["A1"] = riscv.REG_A1
    	register["A2"] = riscv.REG_A2
    	register["A3"] = riscv.REG_A3
    	register["A4"] = riscv.REG_A4
    	register["A5"] = riscv.REG_A5
    	register["A6"] = riscv.REG_A6
    	register["A7"] = riscv.REG_A7
    	register["S2"] = riscv.REG_S2
    	register["S3"] = riscv.REG_S3
    	register["S4"] = riscv.REG_S4
    	register["S5"] = riscv.REG_S5
    	register["S6"] = riscv.REG_S6
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Thu Nov 13 12:17:37 UTC 2025
    - 21.7K bytes
    - Viewed (0)
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