Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 10 of 19 for reg (0.01 sec)

  1. src/cmd/asm/internal/arch/loong64.go

    	}
    
    	if isIndex {
    		arng_type, ok = loong64ElemExtMap[ext]
    		if !ok {
    			return errors.New("Loong64 extension: invalid LSX/LASX arrangement type: " + ext)
    		}
    
    		a.Reg = loong64.REG_ELEM
    		a.Reg += ((reg & loong64.EXT_REG_MASK) << loong64.EXT_REG_SHIFT)
    		a.Reg += ((arng_type & loong64.EXT_TYPE_MASK) << loong64.EXT_TYPE_SHIFT)
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Tue Aug 05 17:31:25 UTC 2025
    - 3.8K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/parse.go

    	// Expect (SB), (FP), (PC), or (SP)
    	p.get('(')
    	reg := p.get(scanner.Ident).String()
    	p.get(')')
    	p.setPseudoRegister(a, reg, isStatic, prefix)
    }
    
    // setPseudoRegister sets the NAME field of addr for a pseudo-register reference such as (SB).
    func (p *Parser) setPseudoRegister(addr *obj.Addr, reg string, isStatic bool, prefix rune) {
    	if addr.Reg != 0 {
    		p.errorf("internal error: reg %s already set in pseudo", reg)
    	}
    	switch reg {
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Fri Feb 14 15:13:11 UTC 2025
    - 37.3K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/arch/arm64.go

    		}
    	} else if reg <= arm64.REG_V31 && reg >= arm64.REG_V0 {
    		switch ext {
    		case "B8":
    			if isIndex {
    				return errors.New("invalid register extension")
    			}
    			a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8B & 15) << 5)
    		case "B16":
    			if isIndex {
    				return errors.New("invalid register extension")
    			}
    			a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_16B & 15) << 5)
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Fri Feb 14 15:13:11 UTC 2025
    - 10.3K bytes
    - Viewed (0)
  4. src/test/java/jcifs/internal/witness/MockWitnessService.java

            // Count how many registrations this affects
            int affectedRegistrations = 0;
            for (MockRegistration reg : registrations.values()) {
                if (reg.shareName.equalsIgnoreCase(resourceName) || reg.serverAddress.equals(resourceName)) {
                    affectedRegistrations++;
                }
            }
    
    Registered: Sun Sep 07 00:10:21 UTC 2025
    - Last Modified: Sat Aug 23 09:06:40 UTC 2025
    - 8.2K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/asm.go

    			// the CR bit.
    			prog.Reg = a[1].Reg
    			if a[1].Type != obj.TYPE_REG {
    				// The CR bit is represented as a constant 0-31. Convert it to a Reg.
    				c := p.getConstant(prog, op, &a[1])
    				reg, success := ppc64.ConstantToCRbit(c)
    				if !success {
    					p.errorf("invalid CR bit register number %d", c)
    				}
    				prog.Reg = reg
    			}
    			break
    		}
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Tue Aug 05 17:31:25 UTC 2025
    - 26.2K bytes
    - Viewed (0)
  6. src/test/java/jcifs/internal/witness/WitnessClientTest.java

            WitnessRegisterResponse mockResponse = mock(WitnessRegisterResponse.class);
            lenient().when(mockResponse.isSuccess()).thenReturn(true);
            lenient().when(mockResponse.getRegistrationId()).thenReturn("test-reg-123");
    
            WitnessRpcClient mockRpc = mock(WitnessRpcClient.class);
            lenient().when(mockRpc.register(any(WitnessRegisterRequest.class))).thenReturn(mockResponse);
    
    Registered: Sun Sep 07 00:10:21 UTC 2025
    - Last Modified: Sat Aug 23 09:06:40 UTC 2025
    - 9.8K bytes
    - Viewed (0)
  7. src/cmd/asm/internal/arch/arm.go

    		return true
    	}
    	return false
    }
    
    // IsARMBFX reports whether the op (as defined by an arm.A* constant) is one the
    // BFX-like instructions which are in the form of "op $width, $LSB, (Reg,) Reg".
    func IsARMBFX(op obj.As) bool {
    	switch op {
    	case arm.ABFX, arm.ABFXU, arm.ABFC, arm.ABFI:
    		return true
    	}
    	return false
    }
    
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Oct 23 15:18:14 UTC 2024
    - 6.1K bytes
    - Viewed (0)
  8. src/cmd/asm/internal/asm/testdata/arm.s

    // MULL r1,r2,(hi,lo)
    //
    //	LTYPEM cond reg ',' reg ',' regreg
    //	{
    //		outcode($1, $2, &$3, int32($5.Reg), &$7);
    //	}
    	MULL	R1, R2, (R3,R4)
    
    //
    // MULA r1,r2,r3,r4: (r1*r2+r3) & 0xffffffff . r4
    // MULAW{T,B} r1,r2,r3,r4
    //
    //	LTYPEN cond reg ',' reg ',' reg ',' spreg
    //	{
    //		$7.Type = obj.TYPE_REGREG2;
    //		$7.Offset = int64($9);
    //		outcode($1, $2, &$3, int32($5.Reg), &$7);
    //	}
    	MULAWT	R1, R2, R3, R4
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 69K bytes
    - Viewed (0)
  9. src/main/java/jcifs/internal/witness/WitnessRegistration.java

        }
    
        /**
         * Generates a unique registration ID.
         *
         * @return a unique registration identifier
         */
        private String generateRegistrationId() {
            return "REG-" + System.currentTimeMillis() + "-" + Integer.toHexString(System.identityHashCode(this));
        }
    
        /**
         * Gets the next sequence number for this registration.
         *
         * @return the next sequence number
    Registered: Sun Sep 07 00:10:21 UTC 2025
    - Last Modified: Mon Aug 25 14:34:10 UTC 2025
    - 6.7K bytes
    - Viewed (0)
  10. schema/constraint.go

    package schema
    
    import (
    	"regexp"
    	"strings"
    
    	"gorm.io/gorm/clause"
    )
    
    // reg match english letters and midline
    var regEnLetterAndMidline = regexp.MustCompile(`^[\w-]+$`)
    
    type CheckConstraint struct {
    	Name       string
    	Constraint string // length(phone) >= 10
    	*Field
    }
    
    func (chk *CheckConstraint) GetName() string { return chk.Name }
    
    func (chk *CheckConstraint) Build() (sql string, vars []interface{}) {
    Registered: Sun Sep 07 09:35:13 UTC 2025
    - Last Modified: Mon Mar 18 07:33:54 UTC 2024
    - 1.9K bytes
    - Viewed (0)
Back to top