FMOVS	F1, 0x44332211(R2)	// FMOVS	F1, 1144201745(R2)
	FMOVD	F1, 0x1007000(R2)	// FMOVD	F1, 16805888(R2)
	FMOVD	F1, 0x44332211(R2)	// FMOVD	F1, 1144201745(R2)
	FMOVQ	F1, 0x1003000(R2)	// FMOVQ	F1, 16789504(R2)
	FMOVQ	F1, 0x44332211(R2)	// FMOVQ	F1, 1144201745(R2)

	MOVB	0x1000000(R1), R2	// MOVB		16777216(R1), R2
	MOVB	0x44332211(R1), R2	// MOVB		1144201745(R1), R2
	MOVH	0x1000000(R1), R2	// MOVH		16777216(R1), R2

        # TF 2.9
        map sigbuild-r2.9 2.9-python3.9
        map sigbuild-r2.9-python3.8 2.9-python3.8
        map sigbuild-r2.9-python3.9 2.9-python3.9
        map sigbuild-r2.9-python3.10 2.9-python3.10
        # TF 2.10
        map sigbuild-r2.10 2.10-python3.9
        map sigbuild-r2.10-python3.8 2.10-python3.8
        map sigbuild-r2.10-python3.9 2.10-python3.9
        map sigbuild-r2.10-python3.10 2.10-python3.10
        # TF 2.11

	BFX	$-2, $4, R2, R3    // ERROR "wrong width or LSB"
	BFXU	$4, R2, R5, R2     // ERROR "missing or wrong LSB"
	BFXU	$4, R2, R5         // ERROR "missing or wrong LSB"
	BFC	$12, $8, R2, R3    // ERROR "illegal combination"
	MOVB	R0>>8, R2          // ERROR "illegal shift"
	MOVH	R0<<16, R2         // ERROR "illegal shift"
	MOVBS	R0->8, R2          // ERROR "illegal shift"
	MOVHS	R0<<24, R2         // ERROR "illegal shift"

	MOVW	R1, 4095(R2)(R3)       // 50132fff
	MOVW	R1, 4096(R2)(R3)       // e31320000150
	MOVWZ	R1, 4095(R2)(R3)       // 50132fff
	MOVWZ	R1, 4096(R2)(R3)       // e31320000150
	MOVH	R1, 4095(R2)(R3)       // 40132fff
	MOVHZ   R1, 4095(R2)(R3)       // 40132fff
	MOVH	R1, 4096(R2)(R3)       // e31320000170
	MOVHZ	R1, 4096(R2)(R3)       // e31320000170
	MOVB	R1, 4095(R2)(R3)       // 42132fff

        MavenArtifactRepositorySubclass r2 = new MavenArtifactRepositorySubclass("foo");
        MavenArtifactRepositorySubclass r3 = new MavenArtifactRepositorySubclass("bar");

        assertTrue(r1.hashCode() == r2.hashCode());
        assertFalse(r1.hashCode() == r3.hashCode());

        assertTrue(r1.equals(r2), "Expected " + r1 + " to equal " + r2);
        assertTrue(r2.equals(r1), "Expected " + r2 + " to equal " + r1);

	CASPD	(R3, R4), (R2), (R8, R9)                         // ERROR "source register pair must start from even register"
	CASPD	(R2, R3), (R2), (R9, R10)                        // ERROR "destination register pair must start from even register"
	CASPD	(R2, R4), (R2), (R8, R9)                         // ERROR "source register pair must be contiguous"

// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

#include "../../../../../runtime/textflag.h"

TEXT asmtest(SB),DUPOK|NOSPLIT,$0
	// ADDV/AND C_DCON32_12S, [r1], r2
	ADDV    $0x27312345fffff800, R4         // ADDV	$2824077224892692480, R4        // 1e00a002be682416decf090384f81000
	ADDV    $0x27312345fffff800, R4, R5     // ADDV	$2824077224892692480, R4, R5    // 1e00a002be682416decf090385f81000

// register parses a full register reference where there is no symbol present (as in 4(R0) or R(10) but not sym(SB))
// including forms involving multiple registers such as R1:R2.
func (p *Parser) register(name string, prefix rune) (r1, r2 int16, scale int8, ok bool) {
	// R1 or R(1) R1:R2 R1,R2 R1+R2, or R1*scale.
	r1, ok = p.registerReference(name)
	if !ok {
		return
	}
	if prefix != 0 && prefix != '*' { // *AX is OK.

func TestCmpReaders(t *testing.T) {
	{
		r1 := bytes.NewReader([]byte("abc"))
		r2 := bytes.NewReader([]byte("abc"))
		ok, msg := cmpReaders(r1, r2)
		if !ok || msg != "" {
			t.Fatalf("unexpected")
		}
	}

	{
		r1 := bytes.NewReader([]byte("abc"))
		r2 := bytes.NewReader([]byte("abcd"))
		ok, _ := cmpReaders(r1, r2)
		if ok {
			t.Fatalf("unexpected")
		}
	}

        if (r1 == r2) {
            return true;
        }

        return Objects.equals(r1.getId(), r2.getId())
                && Objects.equals(r1.getUrl(), r2.getUrl())
                && policyEquals(r1.getPolicy(false), r2.getPolicy(false))
                && policyEquals(r1.getPolicy(true), r2.getPolicy(true));
    }