VLEIG	$1, $32767, V31         // e7f07fff1842
	VSLDB	$3, V1, V16, V18        // e72100030a77
	VERIMB	$2, V31, V1, V2         // e72f10020472
	VSEL	V1, V2, V3, V4          // e7412000308d
	VGFMAH	V21, V31, V24, V0       // e705f10087bc
	VFMADB	V16, V8, V9, V10        // e7a08300948f
	WFMADB	V17, V18, V19, V20      // e74123083f8f
	VFMSDB	V2, V25, V24, V31       // e7f293008b8e

		cfg.Compression.MimeTypes = strings.Split(compress.DefaultMimeTypes, config.ValueSeparator)
	case "30":
		// V30 -> V31
		cfg.OpenID = openid.Config{}
		cfg.Policy.OPA = opa.Args{
			URL:       &xnet.URL{},
			AuthToken: "",
		}
	case "31":
		// V31 -> V32
		cfg.Notify.NSQ = make(map[string]target.NSQArgs)
		cfg.Notify.NSQ["1"] = target.NSQArgs{}
	}

	// Move to latest.

         */
        V20,

        /**
         * Validation for Maven 3.0 POM format.
         */
        V30,

        /**
         * Validation for Maven 3.1 POM format.
         */
        V31,

        /**
         * Validation for Maven 4.0 POM format.
         */
        V40,

        /**
         * Validation for Maven 4.1 POM format.
         */
        V41,

        /**

	VLD2R.P	(R0)(R5), [V31.D1, V0.D1]                       // 1fcce50d
	VLD3R	(RSP), [V31.S2, V0.S2, V1.S2]                   // ffeb400d
	VLD3R.P	6(R15), [V15.H4, V16.H4, V17.H4]                // efe5df0d
	VLD3R.P	(R15)(R6), [V15.H8, V16.H8, V17.H8]             // efe5c64d
	VLD4R	(R0), [V0.B8, V1.B8, V2.B8, V3.B8]              // 00e0600d
	VLD4R.P	16(RSP), [V31.S4, V0.S4, V1.S4, V2.S4]          // ffebff4d

func ARM64RegisterArrangement(reg int16, name, arng string) (int64, error) {
	var curQ, curSize uint16
	if name[0] != 'V' {
		return 0, errors.New("expect V0 through V31; found: " + name)
	}
	if reg < 0 {
		return 0, errors.New("invalid register number: " + name)
	}
	switch arng {
	case "B8":
		curSize = 0
		curQ = 0
	case "B16":
		curSize = 0
		curQ = 1

	MFVSRD VS1, R3                  // 7c230066
	MTFPRD R3, F0                   // 7c030166
	MFVRD V0, R3                    // 7c030067
	MFVSRLD VS63,R4                 // 7fe40267
	MFVSRLD V31,R4                  // 7fe40267
	MFVSRWZ VS33,R4                 // 7c2400e7
	MFVSRWZ V1,R4                   // 7c2400e7
	MTVSRD R3, VS1                  // 7c230166
	MTVSRDD R3, R4, VS1             // 7c232366

// registers in []. There may be comma-separated ranges or individual
// registers, as in [R1,R3-R5] or [V1.S4, V2.S4, V3.S4, V4.S4].
// For ARM, only R0 through R15 may appear.
// For ARM64, V0 through V31 with arrangement may appear.
//
// For 386/AMD64 register list specifies 4VNNIW-style multi-source operand.
// For range of 4 elements, Intel manual uses "+3" notation, for example:
//

	VMOVQ		V7.BU[0], R4    // e480f372
	VMOVQ		V7.BU[1], R4    // e484f372
	VMOVQ		V9.BU[3], R5    // 258df372
	VMOVQ		V10.HU[2], R6   // 46c9f372
	VMOVQ		V11.WU[2], R7   // 67e9f372
	VMOVQ		V31.VU[1], R8   // e8f7f372
	XVMOVQ		X1.W[2], R7     // 27c8ef76
	XVMOVQ		X6.V[2], R8     // c8e8ef76
	XVMOVQ		X8.WU[2], R7    // 07c9f376
	XVMOVQ		X31.VU[2], R8   // e8ebf376

INV V1 // The following macros are used for // the stitched implementation within // counterCryptASM. // Load the initial GCM counter value // in V30 and set up the counter increment // in V31 #define SETUP_COUNTER \ P8_LXVB16X(COUNTER, R0, V30); \ VSPLTISB $1, V28; \ VXOR V31, V31, V31; \ VSLDOI $1, V31, V28, V31 // These macros set up the initial value // for a single encryption, or 4 or 8 // stitched encryptions implemented // with interleaving vciphers. // // The input value for each encryption...