LDPSW	8(R1), (ZR, R2)     // 3f084169
	STP	(R3, R4), (R5)      // a31000a9
	STP	(R3, R4), 8(R5)     // a39000a9
	STP.W	(R3, R4), 8(R5)     // a39080a9
	STP.P	(R3, R4), 8(R5)     // a39080a8
	STP	(R3, R4), -8(R5)    // a3903fa9
	STP	(R3, R4), -4(R5)    // bb1000d1631300a9
	STP	(R3, R4), 11(R0)    // 1b2c0091631300a9
	STP	(R3, R4), 1024(R0)  // 1b001091631300a9
	STP	(R3, R4), (RSP)     // e31300a9

	MOVD.W 	16(R2), R2                                       // ERROR "constrained unpredictable behavior"
	STP	(F2, F3), (R0)                                   // ERROR "invalid register pair"
	STP.W	(R1, R2), 8(R1)                                  // ERROR "constrained unpredictable behavior"
	STP.P	(R1, R2), 8(R2)                                  // ERROR "constrained unpredictable behavior"

</li>

<li>
<code>(R5, R6)</code>: Register pair for <code>LDAXP</code>/<code>LDP</code>/<code>LDXP</code>/<code>STLXP</code>/<code>STP</code>/<code>STP</code>.
</li>

</ul>

<p>
Reference: <a href="/pkg/cmd/internal/obj/arm64">Go ARM64 Assembly Instructions Reference Manual</a>
</p>

<h3 id="ppc64">PPC64</h3>

<p>

		// TODO: Consistency in the encoding would be nice here.
		if p.arch.InFamily(sys.ARM, sys.ARM64) {
			// Special form
			// ARM: destination register pair (R1, R2).
			// ARM64: register pair (R1, R2) for LDP/STP.
			if prefix != 0 || scale != 0 {
				p.errorf("illegal address mode for register pair")
				return
			}
			a.Type = obj.TYPE_REGREG
			a.Offset = int64(r2)
			// Nothing may follow
			return
		}

LDP.P 16(b_ptr), (acc0, acc1) CSEL EQ, acc0, t0, t0 CSEL EQ, acc1, t1, t1 LDP.P 16(b_ptr), (acc2, acc3) CSEL EQ, acc2, t2, t2 CSEL EQ, acc3, t3, t3 CMP $16, const1 BNE loop_select STP (x0, x1), 0*16(res_ptr) STP (x2, x3), 1*16(res_ptr) STP (y0, y1), 2*16(res_ptr) STP (y2, y3), 3*16(res_ptr) STP (t0, t1), 4*16(res_ptr) STP (t2, t3), 5*16(res_ptr) RET /* ---------- // func p256SelectAffine(res *p256AffinePoint, table *p256AffineTable, idx int) TEXT ·p256SelectAffine(SB),NOSPLIT,$0 MOVD idx+16(FP), t0...