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Results 1 - 10 of 19 for Mod64 (0.04 sec)
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src/cmd/compile/internal/ssa/_gen/Wasm.rules
(Div32u x y) => (I64DivU (ZeroExt32to64 x) (ZeroExt32to64 y)) (Div16u x y) => (I64DivU (ZeroExt16to64 x) (ZeroExt16to64 y)) (Div8u x y) => (I64DivU (ZeroExt8to64 x) (ZeroExt8to64 y)) (Div(64|32)F ...) => (F(64|32)Div ...) (Mod64 [false] x y) => (I64RemS x y) (Mod32 [false] x y) => (I64RemS (SignExt32to64 x) (SignExt32to64 y)) (Mod16 [false] x y) => (I64RemS (SignExt16to64 x) (SignExt16to64 y))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 17 03:56:57 UTC 2023 - 16.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/generic.rules
(Mod32 <t> n (Const32 [c])) && isNonNegative(n) && isPowerOfTwo32(c) => (And32 n (Const32 <t> [c-1])) (Mod64 <t> n (Const64 [c])) && isNonNegative(n) && isPowerOfTwo64(c) => (And64 n (Const64 <t> [c-1])) (Mod64 n (Const64 [-1<<63])) && isNonNegative(n) => n // Signed mod by negative constant.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 16 22:21:05 UTC 2024 - 135.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/genericOps.go
// For Mod16, Mod32 and Mod64, AuxInt non-zero means that the divisor has been proved to be not -1. {name: "Mod8", argLength: 2}, // arg0 % arg1, signed {name: "Mod8u", argLength: 2}, // arg0 % arg1, unsigned {name: "Mod16", argLength: 2, aux: "Bool"}, {name: "Mod16u", argLength: 2}, {name: "Mod32", argLength: 2, aux: "Bool"}, {name: "Mod32u", argLength: 2}, {name: "Mod64", argLength: 2, aux: "Bool"},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 42.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(Mod16u x y) => (Mod32u (ZeroExt16to32 x) (ZeroExt16to32 y)) (Mod8 x y) => (Mod32 (SignExt8to32 x) (SignExt8to32 y)) (Mod8u x y) => (Mod32u (ZeroExt8to32 x) (ZeroExt8to32 y)) (Mod64 x y) && buildcfg.GOPPC64 >=9 => (MODSD x y) (Mod64 x y) && buildcfg.GOPPC64 <=8 => (SUB x (MULLD y (DIVD x y))) (Mod64u x y) && buildcfg.GOPPC64 >= 9 => (MODUD x y) (Mod64u x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLD y (DIVDU x y)))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64.rules
(Div16u x y) => (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y)) (Div8 x y) => (DIVV (SignExt8to64 x) (SignExt8to64 y)) (Div8u x y) => (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y)) (Div(32|64)F ...) => (DIV(F|D) ...) (Mod64 x y) => (REMV x y) (Mod64u ...) => (REMVU ...) (Mod32 x y) => (REMV (SignExt32to64 x) (SignExt32to64 y)) (Mod32u x y) => (REMVU (ZeroExt32to64 x) (ZeroExt32to64 y)) (Mod16 x y) => (REMV (SignExt16to64 x) (SignExt16to64 y))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:26:25 UTC 2023 - 31.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64.rules
// (x + y) / 2 => (x / 2) + (y / 2) + (x & y & 1) (Avg64u <t> x y) => (ADD (ADD <t> (SRLI <t> [1] x) (SRLI <t> [1] y)) (ANDI <t> [1] (AND <t> x y))) (Mod64 x y [false]) => (REM x y) (Mod64u ...) => (REMU ...) (Mod32 x y [false]) => (REMW x y) (Mod32u ...) => (REMUW ...) (Mod16 x y [false]) => (REMW (SignExt16to32 x) (SignExt16to32 y))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 40.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64.rules
(Div8 x y) => (Select1 (DIVV (SignExt8to64 x) (SignExt8to64 y))) (Div8u x y) => (Select1 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y))) (Div(32|64)F ...) => (DIV(F|D) ...) (Mod64 x y) => (Select0 (DIVV x y)) (Mod64u x y) => (Select0 (DIVVU x y)) (Mod32 x y) => (Select0 (DIVV (SignExt32to64 x) (SignExt32to64 y))) (Mod32u x y) => (Select0 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y)))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 31 03:59:48 UTC 2023 - 41.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390X.rules
(Div8u x y) => (DIVWU (MOVBZreg x) (MOVBZreg y)) (Hmul(64|64u) ...) => (MULH(D|DU) ...) (Hmul32 x y) => (SRDconst [32] (MULLD (MOVWreg x) (MOVWreg y))) (Hmul32u x y) => (SRDconst [32] (MULLD (MOVWZreg x) (MOVWZreg y))) (Mod64 x y) => (MODD x y) (Mod64u ...) => (MODDU ...) // MODW/MODWU has a 64-bit dividend and a 32-bit divisor, // so a sign/zero extension of the dividend is required. (Mod32 x y) => (MODW (MOVWreg x) y)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 74.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
(Div8u x y) => (UDIVW (ZeroExt8to32 x) (ZeroExt8to32 y)) (Div64u ...) => (UDIV ...) (Div32u ...) => (UDIVW ...) (Div32F ...) => (FDIVS ...) (Div64F ...) => (FDIVD ...) (Mod64 x y) => (MOD x y) (Mod32 x y) => (MODW x y) (Mod64u ...) => (UMOD ...) (Mod32u ...) => (UMODW ...) (Mod(16|8) x y) => (MODW (SignExt(16|8)to32 x) (SignExt(16|8)to32 y))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteWasm.go
v1.AddArg(y) v.AddArg2(v0, v1) return true } } func rewriteValueWasm_OpMod64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (Mod64 [false] x y) // result: (I64RemS x y) for { if auxIntToBool(v.AuxInt) != false { break } x := v_0 y := v_1 v.reset(OpWasmI64RemS) v.AddArg2(x, y) return true }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 17 03:56:57 UTC 2023 - 108.6K bytes - Viewed (0)