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Results 1 - 10 of 24 for Mod8u (0.04 sec)
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src/cmd/compile/internal/ssa/_gen/Wasm.rules
(Mod8 x y) => (I64RemS (SignExt8to64 x) (SignExt8to64 y)) (Mod64u ...) => (I64RemU ...) (Mod32u x y) => (I64RemU (ZeroExt32to64 x) (ZeroExt32to64 y)) (Mod16u x y) => (I64RemU (ZeroExt16to64 x) (ZeroExt16to64 y)) (Mod8u x y) => (I64RemU (ZeroExt8to64 x) (ZeroExt8to64 y)) (And(64|32|16|8|B) ...) => (I64And ...) (Or(64|32|16|8|B) ...) => (I64Or ...) (Xor(64|32|16|8) ...) => (I64Xor ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 17 03:56:57 UTC 2023 - 16.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/generic.rules
(Mod16 (Const16 [c]) (Const16 [d])) && d != 0 => (Const16 [c % d]) (Mod32 (Const32 [c]) (Const32 [d])) && d != 0 => (Const32 [c % d]) (Mod64 (Const64 [c]) (Const64 [d])) && d != 0 => (Const64 [c % d]) (Mod8u (Const8 [c]) (Const8 [d])) && d != 0 => (Const8 [int8(uint8(c) % uint8(d))]) (Mod16u (Const16 [c]) (Const16 [d])) && d != 0 => (Const16 [int16(uint16(c) % uint16(d))])
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 16 22:21:05 UTC 2024 - 135.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64.rules
(Mod32u x y) => (REMVU (ZeroExt32to64 x) (ZeroExt32to64 y)) (Mod16 x y) => (REMV (SignExt16to64 x) (SignExt16to64 y)) (Mod16u x y) => (REMVU (ZeroExt16to64 x) (ZeroExt16to64 y)) (Mod8 x y) => (REMV (SignExt8to64 x) (SignExt8to64 y)) (Mod8u x y) => (REMVU (ZeroExt8to64 x) (ZeroExt8to64 y)) (Select0 <t> (Add64carry x y c)) => (ADDV (ADDV <t> x y) c) (Select1 <t> (Add64carry x y c)) => (OR (SGTU <t> x s:(ADDV <t> x y)) (SGTU <t> s (ADDV <t> s c)))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:26:25 UTC 2023 - 31.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64.rules
(Mod32u ...) => (REMUW ...) (Mod16 x y [false]) => (REMW (SignExt16to32 x) (SignExt16to32 y)) (Mod16u x y) => (REMUW (ZeroExt16to32 x) (ZeroExt16to32 y)) (Mod8 x y) => (REMW (SignExt8to32 x) (SignExt8to32 y)) (Mod8u x y) => (REMUW (ZeroExt8to32 x) (ZeroExt8to32 y)) (And(64|32|16|8) ...) => (AND ...) (Or(64|32|16|8) ...) => (OR ...) (Xor(64|32|16|8) ...) => (XOR ...) (Neg(64|32|16|8) ...) => (NEG ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 40.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS.rules
(Mod32u x y) => (Select0 (DIVU x y)) (Mod16 x y) => (Select0 (DIV (SignExt16to32 x) (SignExt16to32 y))) (Mod16u x y) => (Select0 (DIVU (ZeroExt16to32 x) (ZeroExt16to32 y))) (Mod8 x y) => (Select0 (DIV (SignExt8to32 x) (SignExt8to32 y))) (Mod8u x y) => (Select0 (DIVU (ZeroExt8to32 x) (ZeroExt8to32 y))) // math package intrinsics (Abs ...) => (ABSD ...) // (x + y) / 2 with x>=y becomes (x - y) / 2 + y
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 35.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64.rules
(Mod16 x y) => (Select0 (DIVV (SignExt16to64 x) (SignExt16to64 y))) (Mod16u x y) => (Select0 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y))) (Mod8 x y) => (Select0 (DIVV (SignExt8to64 x) (SignExt8to64 y))) (Mod8u x y) => (Select0 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y))) (Select0 <t> (Add64carry x y c)) => (ADDV (ADDV <t> x y) c) (Select1 <t> (Add64carry x y c)) => (OR (SGTU <t> x s:(ADDV <t> x y)) (SGTU <t> s (ADDV <t> s c)))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 31 03:59:48 UTC 2023 - 41.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/genericOps.go
// For Mod16, Mod32 and Mod64, AuxInt non-zero means that the divisor has been proved to be not -1. {name: "Mod8", argLength: 2}, // arg0 % arg1, signed {name: "Mod8u", argLength: 2}, // arg0 % arg1, unsigned {name: "Mod16", argLength: 2, aux: "Bool"}, {name: "Mod16u", argLength: 2}, {name: "Mod32", argLength: 2, aux: "Bool"}, {name: "Mod32u", argLength: 2},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 42.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(Mod16 x y) => (Mod32 (SignExt16to32 x) (SignExt16to32 y)) (Mod16u x y) => (Mod32u (ZeroExt16to32 x) (ZeroExt16to32 y)) (Mod8 x y) => (Mod32 (SignExt8to32 x) (SignExt8to32 y)) (Mod8u x y) => (Mod32u (ZeroExt8to32 x) (ZeroExt8to32 y)) (Mod64 x y) && buildcfg.GOPPC64 >=9 => (MODSD x y) (Mod64 x y) && buildcfg.GOPPC64 <=8 => (SUB x (MULLD y (DIVD x y))) (Mod64u x y) && buildcfg.GOPPC64 >= 9 => (MODUD x y)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390X.rules
(Mod32 x y) => (MODW (MOVWreg x) y) (Mod32u x y) => (MODWU (MOVWZreg x) y) (Mod16 x y) => (MODW (MOVHreg x) (MOVHreg y)) (Mod16u x y) => (MODWU (MOVHZreg x) (MOVHZreg y)) (Mod8 x y) => (MODW (MOVBreg x) (MOVBreg y)) (Mod8u x y) => (MODWU (MOVBZreg x) (MOVBZreg y)) // (x + y) / 2 with x>=y -> (x - y) / 2 + y (Avg64u <t> x y) => (ADD (SRDconst <t> (SUB <t> x y) [1]) y) (And64 ...) => (AND ...) (And(32|16|8) ...) => (ANDW ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 74.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
(Avg64u ...) => (AVGQU ...) (Mod(64|32|16) [a] x y) => (Select1 (DIV(Q|L|W) [a] x y)) (Mod8 x y) => (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y))) (Mod(64|32|16)u x y) => (Select1 (DIV(Q|L|W)U x y)) (Mod8u x y) => (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))) (And(64|32|16|8) ...) => (AND(Q|L|L|L) ...) (Or(64|32|16|8) ...) => (OR(Q|L|L|L) ...) (Xor(64|32|16|8) ...) => (XOR(Q|L|L|L) ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0)