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Results 1 - 5 of 5 for LDP (0.34 sec)

  1. src/cmd/asm/internal/asm/testdata/arm64error.s

    	CSETM	NV, R2                                           // ERROR "invalid condition"
    	LDP.P	8(R2), (R2, R3)                                  // ERROR "constrained unpredictable behavior"
    	LDP.W	8(R3), (R2, R3)                                  // ERROR "constrained unpredictable behavior"
    	LDP	(R1), (R2, R2)                                   // ERROR "constrained unpredictable behavior"
    	LDP	(R0), (F0, F1)                                   // ERROR "invalid register pair"
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Mar 26 10:48:50 UTC 2025
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  2. src/cmd/asm/internal/asm/testdata/arm64.s

    	LDP	-8(RSP), (R1, R2)   // e18b7fa9
    	LDP	11(RSP), (R1, R2)   // fb2f0091610b40a9
    	LDP	1024(RSP), (R1, R2) // fb031091610b40a9
    	LDP.W	8(RSP), (R1, R2)    // e18bc0a9
    	LDP.P	8(RSP), (R1, R2)    // e18bc0a8
    	LDP	-31(R0), (R1, R2)   // 1b7c00d1610b40a9
    	LDP	-4(R0), (R1, R2)    // 1b1000d1610b40a9
    	LDP	-8(R0), (R1, R2)    // 01887fa9
    	LDP	x(SB), (R1, R2)
    	LDP	x+8(SB), (R1, R2)
    	LDP	8(R1), (ZR, R2)     // 3f8840a9
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Mar 26 10:48:50 UTC 2025
    - 95.3K bytes
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  3. lib/fips140/v1.0.0.zip

    better // 2) CSEL might not be constant time on all ARM processors LDP 0*16(a_ptr), (R4, R5) LDP 1*16(a_ptr), (R6, R7) LDP 2*16(a_ptr), (R8, R9) LDP 0*16(b_ptr), (R16, R17) LDP 1*16(b_ptr), (R19, R20) LDP 2*16(b_ptr), (R21, R22) CSEL EQ, R16, R4, R4 CSEL EQ, R17, R5, R5 CSEL EQ, R19, R6, R6 CSEL EQ, R20, R7, R7 CSEL EQ, R21, R8, R8 CSEL EQ, R22, R9, R9 STP (R4, R5), 0*16(res_ptr) STP (R6, R7), 1*16(res_ptr) STP (R8, R9), 2*16(res_ptr) LDP 3*16(a_ptr), (R4, R5) LDP 4*16(a_ptr), (R6, R7) LDP 5*16(a_ptr),...
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Jan 29 15:10:35 UTC 2025
    - 635K bytes
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  4. src/cmd/asm/internal/asm/parse.go

    	if r2 != 0 {
    		// TODO: Consistency in the encoding would be nice here.
    		if p.arch.InFamily(sys.ARM, sys.ARM64) {
    			// Special form
    			// ARM: destination register pair (R1, R2).
    			// ARM64: register pair (R1, R2) for LDP/STP.
    			if prefix != 0 || scale != 0 {
    				p.errorf("illegal address mode for register pair")
    				return
    			}
    			a.Type = obj.TYPE_REGREG
    			a.Offset = int64(r2)
    			// Nothing may follow
    			return
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Fri Feb 14 15:13:11 UTC 2025
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  5. doc/asm.html

    The other extensions include <code>SXTH</code> (16-bit), <code>SXTW</code> (32-bit), and <code>SXTX</code> (64-bit).
    </li>
    
    <li>
    <code>(R5, R6)</code>: Register pair for <code>LDAXP</code>/<code>LDP</code>/<code>LDXP</code>/<code>STLXP</code>/<code>STP</code>/<code>STP</code>.
    </li>
    
    </ul>
    
    <p>
    Reference: <a href="/pkg/cmd/internal/obj/arm64">Go ARM64 Assembly Instructions Reference Manual</a>
    </p>
    
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Tue Nov 28 19:15:27 UTC 2023
    - 36.3K bytes
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