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Results 1 - 2 of 2 for DIVHW (0.03 sec)

  1. src/cmd/asm/internal/asm/testdata/arm.s

    	XTAHU	R5@>8, R9, R1        // 7514f9e6
    	XTAHU	R5@>16, R9, R1       // 7518f9e6
    	XTAHU	R5@>24, R9, R1       // 751cf9e6
    
    // DIVHW R0, R1, R2: R1 / R0 -> R2
    	DIVHW	R0, R1, R2           // 11f012e7
    	DIVUHW	R0, R1, R2           // 11f032e7
    // DIVHW R0, R1: R1 / R0 -> R1
    	DIVHW	R0, R1               // 11f011e7
    	DIVUHW	R0, R1               // 11f031e7
    
    // misc
    	CLZ	R1, R2         // 112f6fe1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 69K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/arm/asm5.go

    		o1 |= (uint32(p.To.Reg) & 15) << 16
    		o1 |= (uint32(p.From.Reg) & 15) << 8
    		o1 |= (uint32(p.Reg) & 15) << 0
    		o1 |= uint32((p.To.Offset & 15) << 12)
    
    	case 105: /* divhw r,[r,]r */
    		o1 = c.oprrr(p, p.As, int(p.Scond))
    		rf := int(p.From.Reg)
    		rt := int(p.To.Reg)
    		r := int(p.Reg)
    		if r == 0 {
    			r = rt
    		}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 79.4K bytes
    - Viewed (0)
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