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Results 1 - 4 of 4 for CMOVWCC (0.09 sec)
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src/cmd/internal/obj/x86/anames.go
"CMOVQEQ", "CMOVQGE", "CMOVQGT", "CMOVQHI", "CMOVQLE", "CMOVQLS", "CMOVQLT", "CMOVQMI", "CMOVQNE", "CMOVQOC", "CMOVQOS", "CMOVQPC", "CMOVQPL", "CMOVQPS", "CMOVWCC", "CMOVWCS", "CMOVWEQ", "CMOVWGE", "CMOVWGT", "CMOVWHI", "CMOVWLE", "CMOVWLS", "CMOVWLT", "CMOVWMI", "CMOVWNE", "CMOVWOC", "CMOVWOS", "CMOVWPC", "CMOVWPL",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 11 18:32:50 UTC 2023 - 19.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
{name: "CMOVWLS", argLength: 3, reg: gp21, asm: "CMOVWLS", resultInArg0: true}, {name: "CMOVWHI", argLength: 3, reg: gp21, asm: "CMOVWHI", resultInArg0: true}, {name: "CMOVWCC", argLength: 3, reg: gp21, asm: "CMOVWCC", resultInArg0: true}, {name: "CMOVWCS", argLength: 3, reg: gp21, asm: "CMOVWCS", resultInArg0: true}, // CMOV with floating point instructions. We need separate pseudo-op to handle
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 04 16:40:24 UTC 2023 - 98K bytes - Viewed (1) -
src/cmd/compile/internal/ssa/rewriteAMD64.go
v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVWCC x y (InvertFlags cond)) // result: (CMOVWLS x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVWLS) v.AddArg3(x, y, cond) return true } // match: (CMOVWCC _ x (FlagEQ)) // result: x for { x := v_1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 712.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMOVWCC", argLen: 3, resultInArg0: true, asm: x86.ACMOVWCC, reg: regInfo{ inputs: []inputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)